IDT77V1254L25PGI IDT, Integrated Device Technology Inc, IDT77V1254L25PGI Datasheet - Page 37
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IDT77V1254L25PGI
Manufacturer Part Number
IDT77V1254L25PGI
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT77V1254L25PGI.pdf
(48 pages)
Specifications of IDT77V1254L25PGI
Data Rate
25.6/51.2Mbps
Number Of Channels
4
Type Of Atm Phy Interface
DPI/UTOPIA
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Pin Count
144
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT77V1254L25PGI
Manufacturer:
IDT
Quantity:
28
Company:
Part Number:
IDT77V1254L25PGI
Manufacturer:
IDT
Quantity:
621
Low Byte Counter Registers [7:0]
High Byte Counter Registers [15:8]
Counter Select Registers
Interrupt Mask Registers
Addresses: 0x04, 0x14, 0x24, 0x34
[7:0]
Addresses: 0x05, 0x15, 0x25, 0x35
[7:0]
Addresses: 0x06, 0x16, 0x26, 0x36
7
6
5
4
3
2
1
0
Addresses: 0x07, 0x17, 0x27, 0x37
7
6
5
4
3
2
1
0
IDT77V1254L25
Bit
Bit
Bit
Bit
R
R
—
—
—
—
W
W
W
W
R/W
R/W
R/W
R/W
R/W
R/W
Note: For proper operation, only one bit may be set in a Counter Select Register at any time.
Note: When set to "1", these bits mask the corresponding interrupts going to the interrupt pin (INT). When set to "0", the interrupts are
unmasked. These interrupts correspond to the interrupt status bits in the Interrupt Status Registers.
Type
Type
Type
Type
0x00
0x00
—
—
—
—
0
0
0
0
0
0
0 = interrupt enabled
0 = interrupt enabled
0 = interrupt enabled
0 = interrupt enabled
0 = interrupt enabled
0 = interrupt enabled
Initial State
Initial State
Initial State
Initial State
Provides low byte of counter value selected via registers 0x06, 0x16, 0x26, and 0x36
Provides high-byte of counter value selected via registers 0x06, 0x16, 0x26, and 0x36
Reserved.
Reserved.
Reserved.
Reserved.
Symbol Error Counter.
TXCell Counter.
RXCell Counter. Cells with HEC errors are never counted.
Receive HEC Error Counter.
Reserved.
Reserved.
HEC Error Cell.
Short Cell Error.
Transmit Parity Error.
Receive Signal Condition Change.
Receive Cell Symbol Error.
Receive FIFO Overflow.
37 of 48
Function
Function
Function
Function
December 2004