SJA1000/N1 NXP Semiconductors, SJA1000/N1 Datasheet - Page 20

• Manufacturer Part Number: SJA1000/N1
• Manufacturer: NXP Semiconductors

Specifications of SJA1000/N1

• Data Rate: 1000Kbps
• Number Of Transceivers: 1
• Power Down Mode: Sleep
• Standard Supported: CAN 2.0B
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Package Type: PDIP
• Supply Current: 15mA
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Mounting: Through Hole
• Pin Count: 28
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
6.3.9.1
Table 8 ACR bit allocation; can address 4
This register can be accessed (read/write), if the reset
request bit is set HIGH (present). When a message is
received which passes the acceptance test and there is
receive buffer space left, then the respective descriptor
and data field are sequentially stored in the RXFIFO.
When the complete message has been correctly received
the following occurs:
6.3.9.2
Table 9 AMR bit allocation; CAN address 5
This register can be accessed (read/write), if the reset
request bit is set HIGH (present). The acceptance mask
register qualifies which of the corresponding bits of the
acceptance code are ‘relevant’ (AM.X = 0) or ‘don’t care’
(AM.X = 1) for acceptance filtering.
6.3.9.3
The other registers are described in Section 6.5.
2000 Jan 04
The receive status bit is set HIGH (full)
If the receive interrupt enable bit is set HIGH (enabled),
the receive interrupt is set HIGH (set).
Stand-alone CAN controller
BIT 7
BIT 7
AM.7
AC.7
Acceptance Code Register (ACR)
Acceptance Mask Register (AMR)
Other registers
BIT 6
BIT 6
AM.6
AC.6
BIT 5
BIT 5
AM.5
AC.5
BIT 4
BIT 4
AM.4
AC.4
20
The acceptance code bits (AC.7 to AC.0) and the eight
most significant bits of the message’s identifier
(ID.10 to ID.3) must be equal to those bit positions which
are marked relevant by the acceptance mask bits
(AM.7 to AM.0). If the conditions as described in the
following equation are fulfilled, acceptance is given:
(ID.10 to ID.3)
6.4
6.4.1
The CAN controller’s internal registers appear to the CPU
as on-chip memory mapped peripheral registers. Because
the CAN controller can operate in different modes
(operating/reset; see also Section 6.4.3), one has to
distinguish between different internal address definitions.
Starting from CAN address 32 the complete internal RAM
(80-byte) is mapped to the CPU interface.
11111111
BIT 3
BIT 3
AM.3
AC.3
PeliCAN mode
P
ELI
CAN
(AC.7 to AC.0)]
BIT 2
BIT 2
AM.2
AC.2
ADDRESS LAYOUT
BIT 1
BIT 1
AM.1
AC.1
(AM.7 to AM.0)
Product specification
SJA1000
BIT 0
BIT 0
AM.0
AC.0