SJA1000 NXP Semiconductors, SJA1000 Datasheet

SJA1000

Manufacturer Part Number
SJA1000
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SJA1000

Data Rate
1000Kbps
Number Of Transceivers
1
Power Down Mode
Sleep
Standard Supported
CAN 2.0B
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Package Type
PDIP
Supply Current
15mA
Operating Temperature (max)
125C
Operating Temperature (min)
-40C
Operating Temperature Classification
Automotive
Mounting
Through Hole
Pin Count
28
Lead Free Status / RoHS Status
Compliant

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Product specification
Supersedes data of 1999 Aug 17
File under Integrated Circuits, IC18
DATA SHEET
SJA1000
Stand-alone CAN controller
INTEGRATED CIRCUITS
2000 Jan 04

SJA1000 Summary of contents

Page 1

... DATA SHEET SJA1000 Stand-alone CAN controller Product specification Supersedes data of 1999 Aug 17 File under Integrated Circuits, IC18 INTEGRATED CIRCUITS 2000 Jan 04 ...

Page 2

... AC timing diagrams 10.2 Additional AC information 11 PACKAGE OUTLINES 12 SOLDERING 12.1 Introduction 12.2 DIP 12.2.1 Soldering by dipping or by wave 12.2.2 Repairing soldered joints 12.3 SO 12.3.1 Reflow soldering 12.3.2 Wave soldering 12.3.3 Repairing soldered joints 13 DEFINITIONS 14 LIFE SUPPORT APPLICATIONS 2 Product specification SJA1000 ...

Page 3

... SJA1000T SO28 2000 Jan 04 2 GENERAL DESCRIPTION The SJA1000 is a stand-alone controller for the Controller Area Network (CAN) used within automotive and general industrial environments the successor of the PCA82C200 CAN controller (BasicCAN) from Philips Semiconductors. Additionally, a new mode of operation is implemented (PeliCAN) which supports the CAN 2.0B protocol specification with several new features ...

Page 4

... SJA1000 INTERFACE MANAGEMENT LOGIC MESSAGE BUFFER BIT TRANSMIT STREAM BUFFER PROCESSOR RECEIVE FIFO RECEIVE BUFFER ACCEPTANCE FILTER OSCILLATOR Fig.1 Block diagram. 4 Product specification SJA1000 22 V DD1 8 V SS1 internal bus 12 V DD3 15 V SS3 13 TX0 14 TX1 BIT TIMING 19 LOGIC RX0 ...

Page 5

... V supply for input comparator input from the physical CAN-bus line to the input comparator of the SJA1000; a dominant level will wake up the SJA1000 if sleeping; a dominant level is read, if RX1 is higher than RX0 and vice versa for the recessive level; if the CBP bit (see ...

Page 6

... Product specification SJA1000 AD6 1 AD5 28 AD7 AD4 2 27 ALE/AS AD3 AD2 RD/E AD1 AD0 6 V DD1 CLKOUT 7 22 SJA1000T V SS2 V SS1 8 21 XTAL1 9 RX1 20 XTAL2 RX0 DD2 MODE DD3 12 17 RST TX0 INT SS3 TX1 14 15 MGK617 Fig.3 Pin configuration (SO28). ...

Page 7

... It receives error announcements from the BSP and then informs the BSP and IML about error statistics. 6.2 The SJA1000 is designed to be software and pin-compatible to its predecessor, the PCA82C200 stand-alone CAN controller. Additionally, a lot of new functions are implemented. To achieve the software ...

Page 8

... CAN 2.0B The SJA1000 is designed to support the full CAN 2.0B protocol specification, which means that the extended oscillator tolerance is implemented as well as the processing of extended frame messages. In BasicCAN mode it is possible to transmit and receive standard frame messages only (11-bit identifier) ...

Page 9

... RTR and DLC data byte 1 data byte 2 data byte 3 data byte 4 data byte 5 data byte 6 data byte 7 data byte 8 clock divider; note 3 9 Product specification SJA1000 RESET MODE READ WRITE control control (FFH) command status interrupt acceptance code acceptance code ...

Page 10

... TBS Transmit Buffer Status DOS Data Overrun Status RBS Receive Buffer Status reserved reserved reserved WUI Wake-Up Interrupt DOI Data Overrun Interrupt EI Error Interrupt TI Transmit Interrupt RI Receive Interrupt 10 Product specification SJA1000 VALUE SETTING BIT CR.0 BY RESET BY SOFTWARE OR HARDWARE DUE TO BUS-OFF ...

Page 11

... Output Control Transistor P0 OCTN0 Output Control Transistor N0 OCPOL0 Output Control Polarity 0 OCMODE1 Output Control Mode 1 OCMODE0 Output Control Mode 0 TXB Transmit Buffer RXB Receive Buffer CDR Clock Divider Register 11 Product specification SJA1000 VALUE SETTING BIT CR.0 BY RESET BY SOFTWARE OR HARDWARE DUE TO BUS-OFF ...

Page 12

... SJA1000 enabled; when a message has been successfully transmitted or the transmit buffer is accessible again, (e.g. after an abort transmission command) the SJA1000 transmits a transmit interrupt signal to the microcontroller disabled; the microcontroller receives no transmit interrupt signal from the SJA1000 SJA1000 ...

Page 13

... OMMAND EGISTER A command bit initiates an action within the transfer layer of the SJA1000. The command register appears to the microcontroller as a write only memory read access is performed to this address the byte ‘11111111’ is returned. Between two commands at least one internal clock cycle is needed to process. The internal clock is divided by two from the external oscillator frequency ...

Page 14

... Notes 1. The SJA1000 will enter sleep mode if the sleep bit is set to logic 1 (sleep); there is no bus activity and no interrupt is pending. Setting of GTS with at least one of the previously mentioned exceptions valid will result in a wake-up interrupt. After sleep mode is set, the CLKOUT signal continues until at least 15 bit times have passed, to allow a host microcontroller clocked via this signal to enter its own standby mode before the CLKOUT goes LOW. The SJA1000 will wake up when one of the three previously mentioned conditions is negated: after ‘ ...

Page 15

... Philips Semiconductors Stand-alone CAN controller 6.3 (SR) TATUS EGISTER The content of the status register reflects the status of the SJA1000. The status register appears to the microcontroller as a read only memory. Table 5 Bit interpretation of the status register (SR); CAN address 2 BIT SYMBOL SR.7 BS Bus Status; note 1 SR ...

Page 16

... After reading a message stored in the RXFIFO and releasing this memory space with the command release receive buffer, this bit is cleared. If there is another message available within the FIFO this bit is set again with the next bit quantum (t ). scl 2000 Jan 04 16 Product specification SJA1000 ...

Page 17

... FIFO is not empty and the receive interrupt enable bit is set to logic 1 (enabled) reset; this bit is cleared by any read access of the microcontroller . scl SJA1000 ...

Page 18

... The global layout of the transmit buffer is shown in Table 7. The buffer serves to store a message from the microcontroller to be transmitted by the SJA1000 subdivided into a descriptor and data field. The transmit buffer can be written to and read out by the microcontroller in operating mode only. In reset mode a ‘FFH’ is reflected for all bytes. ...

Page 19

... The acceptance filter is defined by the acceptance code register (ACR; see Section 6.3.9.1) and the acceptance mask register (AMR; see Section 6.3.9.2). 19 Product specification SJA1000 receive buffer window MGK618 ...

Page 20

... Starting from CAN address 32 the complete internal RAM (80-byte) is mapped to the CPU interface. 20 Product specification BIT 2 BIT 1 AC.2 AC.1 (AC.7 to AC.0)] (AM.7 to AM.0) BIT 2 BIT 1 AM.2 AM.1 PeliCAN mode P CAN ELI ADDRESS LAYOUT SJA1000 BIT 0 AC.0 BIT 0 AM.0 ...

Page 21

... TX data 1 TX data 4 TX data 2 TX data 5 TX data 3 TX data 6 TX data 4 TX data 7 TX data 5 TX data 8 TX data 6 21 Product specification SJA1000 RESET MODE READ WRITE mode mode (00H) command status interrupt interrupt enable interrupt enable reserved (00H) ...

Page 22

... Some bits are writeable in reset mode only (CAN mode, CBP, RXINTEN and clock off). 2000 Jan 04 OPERATING MODE WRITE TX data 7 TX data 8 clock divider; note 6 22 Product specification SJA1000 RESET MODE READ WRITE reserved (00H) reserved (00H) RX message counter RX buffer start ...

Page 23

... Arbitration Lost Interrupt 0 (reset) EPI Error Passive Interrupt WUI Wake-Up Interrupt DOI Data Overrun Interrupt EI Error Warning Interrupt TI Transmit Interrupt RI Receive Interrupt 23 Product specification SJA1000 VALUE SETTING MOD.0 RESET BY BY SOFTWARE HARDWARE OR DUE TO BUS-OFF 0 (reserved) 0 (reserved) 0 (wake-up) 0 (wake-up) 0 (dual (normal) ...

Page 24

... TSEG2.2 Time Segment 2.2 TSEG2.1 Time Segment 2.1 TSEG2.0 Time Segment 2.0 TSEG1.3 Time Segment 1.3 TSEG1.2 Time Segment 1.2 TSEG1.1 Time Segment 1.1 TSEG1.0 Time Segment 1.0 24 Product specification SJA1000 VALUE SETTING MOD.0 RESET BY BY SOFTWARE HARDWARE OR DUE TO BUS-OFF ...

Page 25

... Transmit Error Counter TXB Transmit Buffer RXB Receive Buffer ACR0 to ACR3 Acceptance Code Registers AMR0 to AMR3 Acceptance Mask Registers RMC RX Message Counter RBSA RX Buffer Start Address CDR Clock Divider Register 25 Product specification SJA1000 VALUE SETTING MOD.0 RESET BY BY SOFTWARE HARDWARE OR DUE TO BUS-OFF ...

Page 26

... CAN controller will perform a successful transmission, even if there is no acknowledge received normal; an acknowledge is required for successful transmission SJA1000 ...

Page 27

... Reset Mode; note 4 Notes 1. The SJA1000 will enter sleep mode if the sleep mode bit is set to logic 1 (sleep); then there is no bus activity and no interrupt is pending. Setting of SM with at least one of the previously mentioned exceptions valid will result in a wake-up interrupt. After sleep mode is set, the CLKOUT signal continues until at least 15 bit times have passed, to allow a host microcontroller clocked via this signal to enter its own standby mode before the CLKOUT goes LOW ...

Page 28

... RXFIFO is released (no action) present; if not already in progress, a pending transmission request is cancelled (absent) present; a message shall be transmitted (absent) SJA1000 ...

Page 29

... CPU may write a message into the transmit buffer locked; the CPU cannot access the transmit buffer; a message is either waiting for transmission the process of being transmitted SJA1000 ...

Page 30

... RXFIFO absent; no data overrun has occurred since the last clear data overrun command was given full; one or more complete messages are available in the RXFIFO empty; no message is available SJA1000 ...

Page 31

... TIE bit is set within the interrupt enable register reset set; this bit is set while the receive FIFO is not empty and the RIE bit is set within the interrupt enable register reset; no more message is available within the RXFIFO SJA1000 ...

Page 32

... CAN controller requests the respective interrupt disabled enabled; when the receive buffer status is ‘full’ the CAN controller requests the respective interrupt disabled SJA1000 ...

Page 33

... VALUE For value and function see Table 18 ID.28 ID.27 ID.26 ID.25 ID.24 ID.23 ID.22 ID.21 ID.20 ID.19 ID.18 SRTR IDE Fig.5 Arbitration lost bit number interpretation. 33 Product specification FUNCTION ID.8 ID.7 ID.6 ID.5 ID.4 ID.3 ID SJA1000 ID.1 ID.0 RTR MGK619 ...

Page 34

... Philips Semiconductors Stand-alone CAN controller start of frame handbook, full pagewidth TX RX ID.28 ID.27 ID.26 ID.25 ID.24 ID.23 ID.22 ID.21 ID.20 ID.19 ID.18 SRTR Fig.6 Example of arbitration lost bit number interpretation; result: ALC = 08. 2000 Jan 04 arbitration lost 34 Product specification SJA1000 IDE MGK620 ...

Page 35

... Product specification SJA1000 FUNCTION arbitration lost in bit 1 of identifier arbitration lost in bit 2 of identifier arbitration lost in bit 3 of identifier arbitration lost in bit 4 of identifier arbitration lost in bit 5 of identifier arbitration lost in bit 6 of identifier arbitration lost in bit 7 of identifi ...

Page 36

... For bit interpretation of bits ECC.4 to ECC.0 see Table 21. Table 20 Bit interpretation of bits ECC.7 and ECC.6 BIT ECC 2000 Jan 04 (ECC) NAME VALUE 1 0 BIT ECC.6 0 bit error 1 form error 0 stuff error 1 other type of error 36 Product specification FUNCTION RX; error occurred during reception TX; error occurred during transmission FUNCTION SJA1000 ...

Page 37

... Note, that a content change of the EWLR is only possible, if the reset mode was entered previously. An error status change (see status register; Table 14) and an error warning interrupt forced by the new register content will not occur until the reset mode is cancelled again. 37 Product specification SJA1000 FUNCTION (EWLR) ARNING ...

Page 38

... BIT 4 BIT 3 EWL.5 EWL.4 EWL.3 (RXERR) BIT 5 BIT 4 BIT 3 RXERR.5 RXERR.4 RXERR.3 (TXERR) BIT 5 BIT 4 BIT 3 TXERR.5 TXERR.4 TXERR.3 38 Product specification SJA1000 BIT 2 BIT 1 BIT 0 EWL.2 EWL.1 EWL.0 BIT 2 BIT 1 BIT 0 RXERR.2 RXERR.1 RXERR.0 BIT 2 BIT 1 BIT 0 TXERR.2 TXERR.1 TXERR.0 ...

Page 39

... TX data byte data byte data byte 8 27 unused 28 unused 39 Product specification TX frame information 17 TX identifier identifier identifier identifier data byte data byte data byte data byte data byte data byte data byte data byte 8 MGK621 b. Extended frame format. SJA1000 ...

Page 40

... ID.25 ID.24 40 Product specification BIT 2 BIT 1 (4) (4) (4) DLC.2 DLC.1 BIT 2 BIT 1 ID.23 ID.22 BIT 2 BIT 1 (3) ( BIT 2 BIT 1 (4) (4) (4) DLC.2 DLC.1 BIT 2 BIT 1 ID.23 ID.22 SJA1000 BIT 0 (4) DLC.0 BIT 0 ID.21 BIT 0 (3) X BIT 0 (4) DLC.0 BIT 0 ID.21 ...

Page 41

... DLC DLC.1 + bus access priority during the arbitration process. 41 Product specification BIT 2 BIT 1 ID.15 ID.14 BIT 2 BIT 1 ID.7 ID.6 BIT 2 BIT 1 (2) ( FUNCTION Identifier (ID) SJA1000 BIT 0 ID.13 BIT 0 ID.5 BIT 0 (3) X ...

Page 42

... Each message is subdivided into a descriptor and a data field. 64-byte message 3 FIFO message 2 release receive buffer command message 1 BIT 5 BIT 4 BIT DLC.3 42 Product specification R ECEIVE BUFFER receive 23 buffer 22 window CAN address MGK622 BIT 2 BIT 1 (3) (3) (3) DLC.2 DLC.1 SJA1000 BIT 0 (3) DLC.0 ...

Page 43

... Product specification BIT 2 BIT 1 ID.23 ID.22 BIT 2 BIT BIT 2 BIT 1 (3) (3) (3) DLC.2 DLC.1 BIT 2 BIT 1 ID.23 ID.22 BIT 2 BIT 1 ID.15 ID.14 BIT 2 BIT 1 ID.7 ID.6 SJA1000 BIT 0 ID.21 BIT 0 0 BIT 0 (3) DLC.0 BIT 0 ID.21 BIT 0 ID.13 BIT 0 ID.5 ...

Page 44

... Note, that the 4 least significant bits of AMR1 and ACR1 are not used. In order to be compatible with future products these bits should be programmed to be ‘don’t care’ by setting AMR1.3, AMR1.2, AMR1.1 and AMR1.0 to logic 1. 44 Product specification SJA1000 BIT 2 BIT 1 (2) RTR 0 Single fi ...

Page 45

... It should be noted that the 2 least significant bits of AMR3 and ACR3 are not used. In order to be compatible with future products these bits should be programmed to be ‘don’t care’ by setting AMR3.1 and AMR3.0 to logic 1. 45 Product specification SJA1000 LSB MSB LSB CAN ADDRESS 19; ACR3 CAN ADDRESS 23 ...

Page 46

... If no data byte filtering is required for filter 1, the four least significant bits of AMR1 and AMR3 have to be set to logic 1 (don’t care). Then both filters are working identically using the standard identifier range including the RTR bit. 46 Product specification SJA1000 LSB MSB LSB CAN ADDRESS 19; ACR3 unused CAN ADDRESS 23 ...

Page 47

... LSB MSB CA 17; ACR1 CA 17; ACR1 21; AMR1 CA 21; AMR1 23; AMR3 ACR = Acceptance Code Register AMR = Acceptance Mask Register CA 19; ACR3 LSB MSB & & 47 Product specification SJA1000 LSB LSB CA 19; ACR3 23; AMR3 (1) = CAN Address 1 logic 1 = accepted logic 0 = not accepted MGK626 ...

Page 48

... CAN ADDRESS 20; AMR0 CAN ADDRESS 21; AMR1 CAN ADDRESS 22; AMR2 CAN ADDRESS 23; AMR3 CAN ADDRESS 18; ACR2 CAN ADDRESS 19; ACR3 MSB LSB MSB & & 48 Product specification SJA1000 LSB ACR = Acceptance Code Register AMR = Acceptance Mask Register LSB 1 logic 1 = accepted logic 0 = not accepted MGK627 ...

Page 49

... RBSA takes effect first after the next positive edge of the internal clock frequency, which is half of the external oscillator frequency. BIT 5 BIT 4 BIT 3 RBSA.5 RBSA.4 RBSA.3 49 Product specification SJA1000 BIT 2 BIT 1 BIT 0 RMC.2 RMC.1 RMC.0 BIT 2 BIT 1 BIT 0 RBSA.2 RBSA ...

Page 50

... The CAN system clock scl BRP BRP BRP ------------ - f XTAL BIT 5 BIT 4 BIT 3 TSEG2.1 TSEG2.0 TSEG1.3 50 Product specification BIT 2 BIT 1 BRP.2 BRP.1 BRP.1 + BRP BIT 2 BIT 1 TSEG1.2 TSEG1.1 FUNCTION SJA1000 BIT 0 BRP.0 BIT 0 TSEG1.0 ...

Page 51

... This register may be accessed (read/write) if the reset mode is active. In operating mode, this register is read only, if the PeliCAN mode is selected. In BasicCAN mode a ‘FFH’ is reflected. BIT 5 BIT 4 BIT 3 OCPOL1 OCTP0 OCTN0 51 Product specification SYNC TSEG1 SEG BIT 2 BIT 1 OCPOL0 OCMODE1 SJA1000 MGK628 BIT 0 OCMODE0 ...

Page 52

... Stand-alone CAN controller handbook, full pagewidth If the SJA1000 is in the sleep mode a recessive level is output on the TX0 and TX1 pins with respect to the contents within the output control register. If the SJA1000 is in the reset state (reset request = HIGH) or the external reset pin RST is pulled LOW the outputs TX0 and TX1 are floating ...

Page 53

... Dominant bits are sent with alternating levels on TX0 and TX1, i.e. the first dominant bit is sent on TX0, the second is sent on TX1, and the third one is sent on TX0 again, and so on. One possible configuration example of the bi-phase output mode timing is shown in Fig.16. 53 Product specification SJA1000 MGK630 ...

Page 54

... In test output mode the level connected reflected at TXn with the next positive edge of the system clock corresponding to the programmed polarity in the output control register. Table 48 shows the relationship between the bits of the output control register and the output pins TX0 and TX1. 2000 Jan 04 54 Product specification SJA1000 MGK631 f osc -------- 2 ...

Page 55

... BIT 2 BIT 1 CD.2 CD.1 SJA1000 (4) TXX float LOW float float LOW float HIGH HIGH float LOW HIGH HIGH LOW BIT 0 CD.0 ...

Page 56

... Clock off Setting this bit allows the external CLKOUT pin of the SJA1000 to be disabled. A write access is possible only in reset mode. If this bit is set, CLKOUT is LOW during sleep mode, otherwise it is HIGH. 6.5.4.3 RXINTEN This bit allows the TX1 output to be used as a dedicated receive interrupt output ...

Page 57

... CONDITIONS note 1 note 1 note 2 note 3 note peak current, permitted for t < 100 ms. The average output OT CONDITION in free air = 40 to +125 C; all voltages referenced to V CONDITIONS MHz; note 1 osc oscillator inactive; note 2 57 Product specification SJA1000 . SS MIN. MAX. UNIT 0.5 +6 +125 C ...

Page 58

... V 10 1.2 mA; note RST = MODE = Product specification MIN. 0.5 +0.8 0.3V 0.5 +0.6 2.0 V 0.7V DD 2.4 V 500 < note 3 DD 0.4 V 0.4 DD < 0.05 0 RX0 = 2.7 V; RX1 = 2 RX1 = XTAL1 = V ; all outputs DD SS SJA1000 MAX. UNIT 0 0 400 ...

Page 59

... Intel mode 20 Intel mode 40 Motorola mode 40 Intel mode 0 Intel mode 0 Motorola mode 0 Intel mode 0 Intel mode 0 Motorola mode 0 100 10 mV; DIF 1.4 V < V < V 1.4 V; I(RX) DD note 2 = input voltage on pins RX0 and RX1. I(RX) 59 Product specification SJA1000 MIN. MAX. UNIT 24 MHz ...

Page 60

... WR) E (pin RD/E) CS 2000 Jan h(AL-A) t RLQV t LLRL t W(R) t CLRL t RHCH Fig.17 Read cycle timing diagram; Intel mode. t h(AL-A) t LLEH t EHQV t su(R-EH) t CLEH t W(E) Fig.18 Read cycle timing diagram; Motorola mode. 60 Product specification RHDZ ELDZ t ELCH SJA1000 MGK632 MGK633 ...

Page 61

... Jan 04 t h(AL-A) t LLWL t DVWH t W(W) t CLWL Fig.19 Write cycle timing diagram; Intel mode. t h(AL-A) t su(i)(D-EL) t LLEH t su(R-EH) t CLEH t W(E) Fig.20 Write cycle timing diagram; Motorola mode. 61 Product specification WHDX t WHLH t WHCH h(i)(EL-D) t ELAH t ELCH SJA1000 MGK634 MGK635 ...

Page 62

... The minimum differential input voltage at the RX pins has to be greater than 32 mV under all conditions to obtain a defined RXD output level. 2000 Jan 04 V DD2 V DD1 INPUT COMPARATOR LOGIC V SS1 V SS2 Fig.21 Optimized noise immunity block diagram. V RXD < Fig.22 Input comparator definitions. 62 Product specification SJA1000 V DD3 TX0 TX1 V SS3 MGK636 32 V RX0 V RX1 (mV) MGK637 ...

Page 63

... REFERENCES JEDEC EIAJ MO-015 SC-510- 3.9 15.80 17.15 2.54 15.24 3.4 15.24 15.90 0.15 0.62 0.10 0.60 0.13 0.60 EUROPEAN PROJECTION Product specification SJA1000 SOT117 ( max. 0.25 1.7 0.68 0.01 0.067 0.63 ISSUE DATE 95-01-14 99-12-27 ...

Page 64

... REFERENCES JEDEC EIAJ MS-013 detail 10.65 1.1 1.1 0.25 0.25 1.4 10.00 0.4 1.0 0.419 0.043 0.043 0.055 0.01 0.01 0.394 0.016 0.039 EUROPEAN PROJECTION Product specification SJA1000 SOT136 ( 0.9 0.1 0 0.035 0.004 0.016 ISSUE DATE 97-05-22 99-12-27 ...

Page 65

... Use a low voltage ( less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 65 Product specification SJA1000 ...

Page 66

... Philips for any damages resulting from such improper use or sale. 2000 Jan 04 PACKAGE suitable not suitable not suitable suitable not recommended not recommended 66 Product specification SJA1000 SOLDERING METHOD (1) WAVE REFLOW (2) suitable (3) suitable suitable (4)(5) suitable ...

Page 67

... Philips Semiconductors Stand-alone CAN controller 2000 Jan 04 NOTES 67 Product specification SJA1000 ...

Page 68

Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. + 101 ...

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