SJA1000 NXP Semiconductors, SJA1000 Datasheet - Page 31

• Manufacturer Part Number: SJA1000
• Manufacturer: NXP Semiconductors

Specifications of SJA1000

• Data Rate: 1000Kbps
• Number Of Transceivers: 1
• Power Down Mode: Sleep
• Standard Supported: CAN 2.0B
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Package Type: PDIP
• Supply Current: 15mA
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Mounting: Through Hole
• Pin Count: 28
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
6.4.6
The interrupt register allows the identification of an interrupt source. When one or more bits of this register are set, a CAN
interrupt will be indicated to the CPU. After this register is read by the CPU all bits are reset except for the receive interrupt
bit.
The interrupt register appears to the CPU as a read only memory.
Table 15 Bit interpretation of the interrupt register (IR); CAN address 3
2000 Jan 04
IR.7
IR.6
IR.5
IR.4
IR.3
IR.2
IR.1
IR.0
Stand-alone CAN controller
BIT
I
NTERRUPT
BEI
ALI
EPI
WUI
DOI
EI
TI
RI
SYMBOL
R
EGISTER
Bus Error Interrupt
Arbitration Lost Interrupt
Error Passive Interrupt
Wake-Up Interrupt;
note 1
Data Overrun Interrupt
Error Warning Interrupt
Transmit Interrupt
Receive Interrupt; note 2
(IR)
NAME
VALUE
31
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
set; this bit is set when the CAN controller detects
an error on the CAN-bus and the BEIE bit is set
within the interrupt enable register
reset
set; this bit is set when the CAN controller lost the
arbitration and becomes a receiver and the ALIE
bit is set within the interrupt enable register
reset
set; this bit is set whenever the CAN controller has
reached the error passive status (at least one
error counter exceeds the protocol-defined level of
127) or if the CAN controller is in the error passive
status and enters the error active status again and
the EPIE bit is set within the interrupt enable
register
reset
set; this bit is set when the CAN controller is
sleeping and bus activity is detected and the
WUIE bit is set within the interrupt enable register
reset
set; this bit is set on a ‘0-to-1’ transition of the data
overrun status bit and the DOIE bit is set within
the interrupt enable register
reset
set; this bit is set on every change (set and clear)
of either the error status or bus status bits and the
EIE bit is set within the interrupt enable register
reset
set; this bit is set whenever the transmit buffer
status changes from ‘0-to-1’ (released) and the
TIE bit is set within the interrupt enable register
reset
set; this bit is set while the receive FIFO is not
empty and the RIE bit is set within the interrupt
enable register
reset; no more message is available within the
RXFIFO
FUNCTION
Product specification
SJA1000