SJA1000 NXP Semiconductors, SJA1000 Datasheet - Page 28

• Manufacturer Part Number: SJA1000
• Manufacturer: NXP Semiconductors

Specifications of SJA1000

• Data Rate: 1000Kbps
• Number Of Transceivers: 1
• Power Down Mode: Sleep
• Standard Supported: CAN 2.0B
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Package Type: PDIP
• Supply Current: 15mA
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Mounting: Through Hole
• Pin Count: 28
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
6.4.4
A command bit initiates an action within the transfer layer of the CAN controller. This register is write only, all bits will
return a logic 0 when being read. Between two commands at least one internal clock cycle is needed in order to proceed.
The internal clock is half of the external oscillator frequency.
Table 13 Bit interpretation of the command register (CMR); CAN address 1
Notes
1. Upon self reception request a message is transmitted and simultaneously received if the acceptance filter is set to
2. Setting the command bits CMR.0 and CMR.1 simultaneously results in sending the transmit message once.
3. This command bit is used to clear the data overrun condition indicated by the data overrun status bit. As long as the
4. After reading the contents of the receive buffer, the CPU can release this memory space in the RXFIFO by setting
2000 Jan 04
CMR.7
CMR.6
CMR.5
CMR.4
CMR.3
CMR.2
CMR.1
CMR.0
Stand-alone CAN controller
the corresponding identifier. A receive and a transmit interrupt will indicate correct self reception (see also self test
mode in mode register).
No re-transmission will be performed in the event of an error or arbitration lost (single-shot transmission).
Setting the command bits CMR.4 and CMR.1 simultaneously results in sending the transmit message once using the
self reception feature. No re-transmission will be performed in the event of an error or arbitration lost.
Setting the command bits CMR.0, CMR.1 and CMR.4 simultaneously results in sending the transmit message once
as described for CMR.0 and CMR.1.
The moment the transmit status bit is set within the status register, the internal transmission request bit is cleared
automatically.
Setting CMR.0 and CMR.4 simultaneously will ignore the set CMR.4 bit.
data overrun status bit is set no further data overrun interrupt is generated.
the release receive buffer bit to logic 1. This may result in another message becoming immediately available within
the receive buffer. If there is no other message available, the receive interrupt bit is reset.
BIT
C
OMMAND
SRR
CDO
RRB
AT
TR
SYMBOL
R
EGISTER
reserved
reserved
reserved
Self Reception Request;
notes 1 and 2
Clear Data Overrun;
note 3
Release Receive Buffer;
note 4
Abort Transmission;
notes 5 and 2
Transmission Request;
notes 6 and 2
(CMR)
NAME
VALUE
28
1
0
1
0
1
0
1
0
1
0
present; a message shall be transmitted and
received simultaneously
clear; the data overrun status bit is cleared
released; the receive buffer, representing the
message memory space in the RXFIFO is
released
present; if not already in progress, a pending
transmission request is cancelled
present; a message shall be transmitted
(absent)
(no action)
(no action)
(absent)
(absent)
FUNCTION
Product specification
SJA1000