SJA1000 NXP Semiconductors, SJA1000 Datasheet - Page 13

• Manufacturer Part Number: SJA1000
• Manufacturer: NXP Semiconductors

Specifications of SJA1000

• Data Rate: 1000Kbps
• Number Of Transceivers: 1
• Power Down Mode: Sleep
• Standard Supported: CAN 2.0B
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Package Type: PDIP
• Supply Current: 15mA
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Mounting: Through Hole
• Pin Count: 28
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
Notes
1. Any write access to the control register has to set this bit to logic 0 (reset value is logic 0).
2. In the PCA82C200 this bit was used to select the synchronization mode. Because this mode is not longer
3. Reading this bit will always reflect a logic 1.
4. During a hardware reset or when the bus status bit is set to logic 1 (bus-off), the reset request bit is set to logic 1
6.3.4
A command bit initiates an action within the transfer layer of the SJA1000. The command register appears to the
microcontroller as a write only memory. If a read access is performed to this address the byte ‘11111111’ is returned.
Between two commands at least one internal clock cycle is needed to process. The internal clock is divided by two from
the external oscillator frequency.
2000 Jan 04
CR.1
CR.0
Stand-alone CAN controller
implemented, setting this bit has no influence on the microcontroller. Due to software compatibility setting this bit is
allowed. This bit will not change after hardware or software reset. In addition the value written by users software is
reflected.
(present). If this bit is accessed by software, a value change will become visible and takes effect first with the next
positive edge of the internal clock which operates with
the microcontroller cannot set the reset request bit to logic 0 (absent). Therefore, after having set the reset request
bit to logic 0, the microcontroller must check this bit to ensure that the external reset pin is not being held LOW.
Changes of the reset request bit are synchronized with the internal divided clock. Reading the reset request bit
reflects the synchronized status.
After the reset request bit is set to logic 0 the SJA1000 will wait for:
a) One occurrence of bus-free signal (11 recessive bits), if the preceding reset request has been caused by a
b) 128 occurrences of bus-free, if the preceding reset request has been caused by a CAN controller initiated bus-off,
BIT
hardware reset or a CPU-initiated reset
before re-entering the bus-on mode; it should be noted that several registers are modified if the reset request bit
was set (see also Table 2).
C
OMMAND
RIE
RR
SYMBOL
R
EGISTER
Receive Interrupt Enable
Reset Request; note 4
(CMR)
NAME
VALUE
1
13
1
0
1
0
2
of the external oscillator frequency. During an external reset
enabled; when a message has been received
without errors, the SJA1000 transmits a receive
interrupt signal to the microcontroller
disabled; the microcontroller receives no transmit
interrupt signal from the SJA1000
present; detection of a reset request results in
aborting the current transmission/reception of a
message and entering the reset mode
absent; on the ‘1-to-0’ transition of the reset
request bit, the SJA1000 returns to the operating
mode
FUNCTION
Product specification
SJA1000