KSZ8995M A4 Micrel Inc, KSZ8995M A4 Datasheet - Page 18

• Manufacturer Part Number: KSZ8995M A4
• Manufacturer: Micrel Inc

Specifications of KSZ8995M A4

• Number Of Primary Switch Ports: 5
• Internal Memory Buffer Size: 64
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 1.9/2.6/3.6V
• Operating Supply Voltage (min): 1.7/2.4/3V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Compliant

KS8995M
M9999-062309
Note:
1. P = Power supply
Pin Number
I = Input
O = Output
I/O = Bi-directional
Gnd = Ground
Ipu = Input w/ internal pull-up
Ipd = Input w/ internal pull-down
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise
PU = Strap pin pull-up
PD = Strap pin pull-down
Otri = Output tristated
NC = No Connect
87
86
85
78
83
82
81
80
79
75
73
72
71
70
69
74
Pin Name
SMRXDV
SMRXD0
SMRXD1
SMRXD2
SMRXD3
SMTXEN
SMTXER
SCONF0
SCONF1
SMTXD0
SMTXD1
SMTXD2
SMTXD3
SMRXC
SMTXC
SCRS
Type
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
I/O
I/O
(1)
Port
Pin Function
Dual MII configuration pin
Dual MII configuration pin
Pin# (91, 86, 87):
000
001
010
011
100
101
110
111
Switch MII carrier sense
Switch MII receive clock. Input in MAC mode, output in PHY mode MII.
Switch MII receive bit 0; Strap option: LED Mode
PD (default) = Mode 0; PU = Mode 1. See “Register 11.”
LEDX_2
LEDX_1
LEDX_0
Switch MII receive bit 1. Strap option: PD (default) = Switch MII in
100Mbps mode; PU = Switch MII in 10Mbps mode.
Switch MII receive bit 2. Strap option: PD (default) = Switch MII in
full-duplex mode; PU = Switch MII in half-duplex mode.
Switch MII receive bit 3. Strap option: PD (default) = Disable Switch
MII full-duplex flow control; PU = Enable Switch MII full-duplex flow control.
Switch MII receive data valid
Switch MII transmit clock. Input in MAC mode, output in PHY mode MII.
Switch MII transmit bit 0
Switch MII transmit bit 1
Switch MII transmit bit 2
Switch MII transmit bit 3
Switch MII transmit enable
Switch MII transmit error
18
Switch MII
Disable, Otri
PHY Mode MII
MAC Mode MII
PHY Mode SNI
Disable
PHY Mode MII
MAC Mode MII
PHY Mode SNI
PHY [5] MII
Disable, Otri
Disable, Otri
Disable, Otri
Disable, Otri
Disable
PHY Mode MII
PHY Mode MII
PHY Mode MII
Mode 0
Lnk/Act
Fulld/Col
Speed
Mode 1
100Lnk/Act
10Lnk/Act
Fulld
Micrel, Inc.
June 2009