KSZ8995M A4 Micrel Inc, KSZ8995M A4 Datasheet - Page 47

• Manufacturer Part Number: KSZ8995M A4
• Manufacturer: Micrel Inc

Specifications of KSZ8995M A4

• Number Of Primary Switch Ports: 5
• Internal Memory Buffer Size: 64
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 1.9/2.6/3.6V
• Operating Supply Voltage (min): 1.7/2.4/3V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Compliant

June 2009
KS8995M
Register 24 (0x18): Port 1 Control 8
Register 40 (0x28): Port 2 Control 8
Register 56 (0x38): Port 3 Control 8
Register 72 (0x48): Port 4 Control 8
Register 88 (0x58): Port 5 Control 8
Address
7-0
Register 25 (0x19): Port 1 Control 9
Register 41 (0x29): Port 2 Control 9
Register 57 (0x39): Port 3 Control 9
Register 73 (0x49): Port 4 Control 9
Register 89 (0x59): Port 5 Control 9
Address
7-0
Register 26 (0x1A): Port 1 Control 10
Register 42 (0x2A): Port 2 Control 10
Register 58 (0x3A): Port 3 Control 10
Register 74 (0x4A): Port 4 Control 10
Register 90 (0x5A): Port 5 Control 10
Address
7-4
3-0
Register 27 (0x1B): Port 1 Control 11
Register 43 (0x2B): Port 2 Control 11
Register 59 (0x3B): Port 3 Control 11
Register 75 (0x4B): Port 4 Control 11
Register 91 (0x5B): Port 5 Control 11
Address
7
6
5
4
Name
Receive high priority
rate control [7:0]
Name
Receive low priority
rate control [7:0]
Name
Receive low priority
rate control [11:8]
Receive high priority
rate control [11:8]
Name
Receive differential
priority rate control
Low priority receive
rate control enable
High priority receive
rate control enable
Low priority receive rate
flow control enable
Description
This along with port control 10, bits [3:0] form a 12-bit
field to determine how many “32Kbps” high priority
blocks can be received. (In a unit of 4K bytes in a one
second period.)
Description
This along with port control 10, bits [7:4] form a 12-bit
field to determine how many “32Kbps” low priority
blocks can be received. (In a unit of 4K bytes in a one
second period.)
Description
This along with port control 9, bits [7:0] form a 12-bit
field to determine how many “32Kbps” low priority
blocks can be received. (In a unit of 4K bytes in a one
second period.)
This along with port control 8, bits [7:0] form a 12-bit
field to determine how many “32Kbps” high priority
blocks can be received. (In a unit of 4K bytes in a one
second period.)
Description
1, If bit 6 is also ‘1’ this will enable receive rate control
for this port on low priority packets at the low priority
rate. If bit 5 is also ‘1’, this will enable receive rate
control on high priority packets at the high priority rate
0, receive rate control will be based on the low priority
rate for all packets on this port.
1, enable port’s low priority receive rate control feature.
0, disable port’s low priority receive rate control.
1, If bit 7 is also ‘1’ this will enable the port’s high
priority receive rate control feature. If bit 7 is a ‘0’ and
bit 6 is a ‘1’, all receive packets on this port will be rate
controlled at the low priority rate.
0, disable port’s high priority receive rate control feature.
1, flow control may be asserted if the port’s low priority
receive rate is exceeded.
0, flow control is not asserted if the port’s low priority
receive rate is exceeded.
47
Mode
R/W
Mode
R/W
Mode
R/W
R/W
Mode
R/W
R/W
R/W
R/W
Default
0
Default
0
Default
0
0
Default
0
0
0
0
M9999-062309
Micrel, Inc.