82V2048SBB IDT, Integrated Device Technology Inc, 82V2048SBB Datasheet - Page 25

• Manufacturer Part Number: 82V2048SBB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2048SBB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Table-14 Parallel Host Interface Pins
IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION
are configured properly. The required sequence for configuring the
Inband Loopback Generator is: First, set registers e-LBAC and e-LBDC,
followed by register e-LBCF. Then, to select the Inband Loopback
generator set registers e-LBGS and then e-LBGE.
tion can not be used simultaneously.
interrupts):
2.18.2 SERIAL HOST INTERFACE
host Mode. In this mode, the registers are accessible through a 16-bit
word which contains an 8-bit command/address byte (bit R/W and 5-
address-bit A1~A5, A6 and A7 bits are ignored) and a subsequent 8-bit
The Inband Loopback Detection and the Inband Loopback Genera-
Example: 5-bit Loop-up/Loop-down Detection (w/o interrupts):
(see note in register description for e-LBAC)
Set (in this order)
Example: 5-bit Loop-up/Loop-down Activation on Channel 1 (w/o
Set (in this order)
By pulling pin MODE2 to VDDIO/2, the device operates in the serial
Loop-up code: 11000
Loop-down code: 11100
e-LBAC (0x09) = 0xC6 (11000110)
e-LBDC (0x0A) = 0xE7 (11100111)
e-LBCF (0x08) = 0x30
Loop-up code: 11000
Loop-down code: 11100
e-LBAC (0x09) = 0xC6 (11000110)
MODE[2:0]
101
110
111
100
SDO
CS
SCLK
SDI
1. While R/W=1, read from IDT82V2048S; While R/W=0, write to IDT82V2048S.
2. Ignored.
R/W
Figure-21 Serial Host Mode Timing
1
A1
Address/Command Byte
Non-multiplexed Motorola interface
High Impedance
A2
Non-multiplexed Intel interface
Multiplexed Motorola interface
Multiplexed Intel interface
A3
Host Interface
A4 A5 A6
25
2
A7
2.18 HOST INTERFACE
the device. The interface consists of serial host interface and parallel
host interface. By pulling pin MODE2 to VDDIO/2 or high, the device can
be set to work in serial mode and in parallel mode respectively.
2.18.1 PARALLEL HOST INTERFACE
MODE1 and MODE0 are used to select the operating mode of the
parallel host interface. When pin MODE1 is pulled low, the host uses
separate address bus and data bus. When high, multiplexed address/
data bus is used. When pin MODE0 is pulled low, the parallel host inter-
face is configured for Motorola compatible hosts. When pin MODE0 is
pulled high, the parallel host interface is configured for Intel compatible
hosts. See
pins in each operation mode is tabulated in Table-14:
data byte (D7~D0), as shown in Figure-21. When bit R/W is set to ‘1’,
data is read out from pin SDO. When bit R/W is set to ‘0’, data on pin
SDI is written into the register whose address is indicated by address
bits A5~A1. See
2
D0 D1 D2 D3 D4 D5 D6 D7
The host interface provides access to read and write the registers in
The interface is compatible with Motorola and Intel host. Pins
D0 D1 D2 D3 D4 D5 D6 D7
Driven while R/W=1
e-LBDC (0x0A) = 0xE7 (11100111)
e-LBCF (0x08) = 0x00
e-LBGS (0x0E) = 0x00
e-LBGE (0x0F) = 0x02
Input Data Byte
Table-1 Pin Description
Figure-21 Serial Host Mode
CS, RDY, WR, RD, ALE, A[4:0], D[7:0], INT
INDUSTRIAL TEMPERATURE RANGES
CS, ACK, DS, R/W, AS, A[4:0], D[7:0], INT
Generic Control, Data and Output Pin
CS, RDY, WR, RD, ALE, AD[7:0], INT
CS, ACK, DS, R/W, AS, AD[7:0], INT
for more details. The host interface
Timing.