TTSV04622V2-DB LSI, TTSV04622V2-DB Datasheet - Page 39

• Manufacturer Part Number: TTSV04622V2-DB
• Manufacturer: LSI

Specifications of TTSV04622V2-DB

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

May 2001
Overview
Frame Pulse
If SYS_CLK rises in under 2 ns after the rising edge of
the frame pulse, the SYS_CLK will not sample the
frame pulse until its next rising edge.
The frame pulse detection is configured by a device-
level control bit (FP_MODE). The frame pulse can be a
one (or more) clock wide pulse or it can be an eight (or
more) clock wide pulse (in reference to the 155.52 MHz
system clock). For normal operation, the device can be
set to one or more clocks. If the frame pulse comes
from a source that encodes the S1 byte onto the frame
pulse signal with manchester encoding, then the frame
pulse detection must be set to four or more clocks. This
ensures that the manchester-encoded S1 does not
interfere with framing.
Microprocessor Interface
Architecture
The TDCS4810G microprocessor interface architec-
ture is configured for glueless interface to two specific
microprocessors, the Motorola MPC860 and the
MC68360, and to the Motorola DSP56309 digital signal
processor; however, other processors may also be
used, as long as the bus cycles comply with those of
the MPC860, DSP56309, or the MC68360. Bus trans-
fers using the MC68360 are asynchronous, while the
MPC860 and DSP56309 transfers are synchronous to
the processor clock. When the MPC860 is used, parity
is generated and checked on the data bus.
The microprocessor interface operates at the fre-
quency of the microprocessor clock (PCLK) input. The
state of the MPMODE input signal determines whether
bus transfers are synchronous or asynchronous with
respect to PCLK.
The TDCS4810G has a separate 13-bit wide address
bus and a 16-bit wide data bus. The microprocessor
interface generates an external processor bus error
(from pin TEA_N) if an internal data acknowledgment is
not received in a predetermined period of time or on
parity errors.
Transfer Error Acknowledge (Pin TEA_N)
The TDCS4810G contains a bus time-out counter.
When this counter saturates, a bus error is generated
to the external processor through the transfer error
acknowledge signal pin TEA_N. This feature must be
considered with respect to the external processor’s
Agere Systems Inc.
(continued)
(continued)
ability to generate its own internal bus time-out. Trans-
fer error acknowledge will be asserted if an internal
data acknowledgment is not received within 32 PCLK
periods of the start of the access. This interval is used
since all valid internal accesses to the device will be
completed in significantly less than 32 PCLK periods.
(See Table 6, page 26.)
Transfer error acknowledge is also asserted if the cal-
culated parity value does not match the parity gener-
ated by the external microprocessor on a data transfer.
The generation of transfer error acknowledge on parity
errors can be disabled by setting the MPMODE bits to
11.
Interrupt Structure
The interrupt structure of the TDCS4810G is designed
to minimize the effort for software/firmware to isolate
the interrupt source. The interrupt structure is com-
prised of different registers depending on the consoli-
dation level. At the lowest level (source level), there are
two registers. The first is an alarm register (AR). An
alarm register is typically of the write 1 clear (W1C)
type. The second is an interrupt mask (IM) register of
the read/write (RW) type.
An alarm register latches a raw status alarm. This
latched alarm may contribute to an interrupt if its corre-
sponding interrupt mask bit is disabled. Individual
latched alarms are consolidated into an interrupt status
register (ISR). If any of the latched alarms that are con-
solidated into a bit of an ISR are set and unmasked,
the ISR bit is set. The ISR bit may contribute to an
interrupt if its corresponding interrupt mask bit is dis-
abled. ISRs may be consolidated into higher-level ISR
in a similar fashion until all alarms are consolidated into
the chip-level ISR. The alarm register that causes an
interrupt can be determined by traversing the tree of
ISRs, starting at the chip-level ISR, until the source
alarm is found.
Note: Interrupts are masked when the corresponding
Powerdown Mode
In powerdown mode, clocks are stopped from toggling
whenever clock gating is possible. When clock gating
is not possible, logic is inhibited from toggling by either
using clock enable signals on flip-flops, or by forcing
data paths to all ones.
The CDR block should also be powered down.
bit in the mask register is 1. If the mask register
bit is 0, then the interrupt is enabled.
10 Gbits/s APS Port and TSI
39