TTSV04622V2-DB LSI, TTSV04622V2-DB Datasheet - Page 7

• Manufacturer Part Number: TTSV04622V2-DB
• Manufacturer: LSI

Specifications of TTSV04622V2-DB

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

May 2001
Description
Receive Interface
The receiver is composed of 48 STS-12 channels that
are either treated as independent channels, or treated
as three groups of 16 channels each, forming three
STS-192 streams. Incoming data for each channel is
received through an LVDS serial port operating at
622 Mbits/s. The incoming serial stream frequency
must be the same as the outgoing LVDS serial stream
of the transmitter. Each STS-192 interface (16 chan-
nels) has its own PLL using the same reference clock.
The receiver is able to handle STS-12 streams having
combined static and dynamic frame offsets of up to
64 bytes without creating any traffic disruption.
The receiver performs three major functions, which are
described in greater detail in upcoming sections: the
clock and data recovery (CDR), the framer, and the
FIFO aligner.
Fabric Core
The cross connect has 48 input channels and 48 out-
put channels. Each channel has the bandwidth capac-
ity to carry an STS-12 worth of data. The channels can
also be thought of as three bidirectional STS-192 data
streams.
The fabric core consists of a time-slot interchanger
(TSI), a connection memory (shown externally in
Figure 1), E1/F1/E2 extraction, and AIS/UNEQ inser-
tion.
Time-Slot Interchanger (TSI)
The TSI is used to reorder the STS-1 data. In doing
this, the TSI ensures that any output STS-1 channel
can be connected to any input STS-1 regardless of any
other switch configuration. Incoming data is written into
one of two buffers in a regular order while output data
is read from another buffer in an order dependent on
the address provided to the TSI, from the connection
memory, for each channel. Once one buffer has been
completely written to, the read and write buffers switch.
This switch is controlled by a synchronization input.
Connection Memory
The connection memory is used to configure the TSI to
switch the incoming STS-1s to the desired output
buffer. There is a working memory to configure the
working connections for each STS-1, and there is a
protected memory to configure the protection connec-
tion for each STS-1. Each of the working and protected
memories are duplicated (A and B) to allow for easy
Agere Systems Inc.
(continued)
software configuration.
E1/F1/E2 Extraction
The E1 and F1 bytes of each STS-1 carry information
indicating the path status of that STS-1. Both bytes
contain the same information. This information can be
used by software to initiate a switch from working to
protected configurations. The E1 and F1 bytes are
extracted from STS-1s at the output of the TSI and
stored.
The bytes are monitored for a change, and if a change
is detected, a latched alarm is raised.
The E2 byte of the STS-1 of each STS-12 (channel)
carries proprietary information indicating the line status
of that STS-12. This information can be used by soft-
ware to initiate a switch from working to protected con-
figurations. The E2 byte is extracted from the STS-1 of
each STS-12 at the input to the TSI and stored.
AIS/UNEQ Insertion
Path AIS(AIS-P) and UNEQ indications can be inserted
on individual STS-1s within a stream under software
control to squelch individual STS-1s during and after
network topology reconfigurations. This process
ensures that downstream path processors will detect a
normal pointer and will thus be able to extract the path
overhead in order to detect an UNEQ defect.
Transmit Interface
The transmitter is composed of 48 STS-12 channels
that are always treated as independent channels.
Incoming data for each channel is received from the
cross connect. Each of the outgoing LVDS serial
streams of the transmitter transmits at a rate of
622 Mbits/s, and the data is synchronized to the sys-
tem clock.
Microprocessor Interface
The microprocessor interface supports both synchro-
nous and asynchronous operations. The microproces-
sor interface has a 16-bit wide data bus and a 13-bit
wide address bus.
Channels can be independently enabled or disabled
under software control with powerdown mode. In the
event that redundant cross connects are desired,
3-state buffers are available to support redundancy.
Supervisory features built into the TDCS4810G provide
diagnostic capabilities and fault coverage. There is an
interrupt output for the microprocessor interface. Inter-
rupt sources are maskable.
10 Gbits/s APS Port and TSI
7