82V2088DR IDT, Integrated Device Technology Inc, 82V2088DR Datasheet - Page 51

• Manufacturer Part Number: 82V2088DR
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2088DR

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

OCTAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
4.2.7
Table-50 STAT0: Line Status Register 0 (real time status monitor)
TCLK_LOS
IBLBD_S
IBLBA_S
PRBS_S
Symbol
EQ_S
LINE STATUS REGISTERS
(R, Address = 14H,34H,54H,74H,94H,B4H,D4H,F4H)
Bit
5
4
7
6
3
Default
0
0
0
0
0
Inband Loopback deactivate code receive status indication
Synchronous status indication of PRBS/QRSS (real time)
Equalizer status indication
= 0: In range
= 1: out of range
Inband Loopback activate code receive status indication
= 0: no Inband Loopback activate code is detected
= 1: activate code has been detected for more than t ms. Even there is bit error, this bit remains set as long as the
bit error rate is less than 10
Note1:
Automatic remote loopback switching is disabled (ARLP = 0), t = 40 ms. If automatic remote loopback switching is
enabled (ARLP = 1), t = 5.1 s. The rising edge of this bit activates the remote loopback operation in local end.
Note2:
If IBLBA_IM=0 and IBLBA_IES=0, a ‘0’ to ‘1’ transition on this bit will cause an activate code detect interrupt.
If IBLBA_IM=0 and IBLBA_IES=1, any changes on this bit will cause an activate code detect interrupt.
= 0: no Inband Loopback deactivate code is detected
= 1: the Inband Loopback deactivate code has been detected for more than t. Even there is a bit error, this bit
remains set as long as the bit error rate is less than 10
Note1:
Automatic remote loopback switching is disabled (ARLP = 0), t = 40 ms.If automatic remote loopback switching is
enabled (ARLP = 1), t= 5.1 s. The rising edge of this bit disables the remote loopback operation.
Note2:
If IBLBD_IM=0 and IBLBD_IES=0, a ‘0’ to ‘1’ transition on this bit will cause a deactivate code detect interrupt.
If IBLBD_IM=0 and IBLBD_IES=1, any changes on this bit will cause a deactivate code detect interrupt.
= 0: 2
= 1: 2
Note:
If PRBS_IM=0 and PRBS_IES=0, a ‘0’ to ‘1’ transition on this bit will cause a synchronous status detect interrupt.
If PRBS_IM=0 and PRBS_IES=1, any changes on this bit will cause a synchronous status detect interrupt.
TCLKn loss indication
= 0: normal
= 1: TCLKn pin has not toggled for more than 70 MCLK cycles.
Note:
If TCLK_IM=0 and TCLK_IES=0, a ‘0’ to ‘1’ transition on this bit will cause an interrupt.
If TCLK_IM=0 and TCLK_IES=1, any changes on this bit will cause an interrupt.
15
15
-1 (E1) PRBS or 2
-1 (E1) PRBS or 2
20
20
-2
-1 (T1/J1) QRSS is not detected
-1 (T1/J1) QRSS is detected.
.
51
Description
-2
.
TEMPERATURE RANGES
INDUSTRIAL