WG82574IT S LBAB Intel, WG82574IT S LBAB Datasheet - Page 107
WG82574IT S LBAB
Manufacturer Part Number
WG82574IT S LBAB
Description
Manufacturer
Intel
Datasheet
1.WG82574IT_S_LBAB.pdf
(472 pages)
Specifications of WG82574IT S LBAB
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Compliant
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Non-Volatile Memory (NVM) Map—82574 GbE Controller
6.2.1.16
6.2.1.17
PCIe Init Configuration 1 Word (Word 0x18)
PCIe Init Configuration 2 Word (Word 0x19)
15
14:12
11:9
8:6
5:3
2:0
15
14
13
12
11:8
7:0
Bit
Bit
Reserved
L1_Act_Ext_Latency
L1_Act_Acc_Latency
L0s_Acc_Latency
L0s_Se_Ext_Latency
L0s_Co_Ext_Latency
DLLP timer
enable
Reserved
Reserved
SER_EN
ExtraNFTS
NFTS
Name
Name
0b
0b
1b
0b
0x1
0x50
Default
0b
110b
(32s-
64s)
110b
(32s-
64s)
011b
(512ns)
001b
001b
Default
When set, enables the DLLP timer counter.
Reserved
Reserved
When set to 1b, the serial number capability is enabled.
Extra NFTS (number of fast training signal), which is added to the
original requested number of NFTS (as requested by the upstream
component).
Number of special sequence for L0s transition to L0.
Reserved
L1 active exit latency for the configuration space.
L1 active acceptable latency for the configuration space.
L0s acceptable latency for the configuration space.
L0s exit latency for active state power management (separated
reference clock) – (latency between 64 ns – 128 ns).
L0s exit latency for active state power management (common
reference clock) – (latency between 64 ns – 128 ns).
Description
Description
107
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