ADM6996L-AA-T-1 Lantiq, ADM6996L-AA-T-1 Datasheet - Page 11

• Manufacturer Part Number: ADM6996L-AA-T-1
• Manufacturer: Lantiq

Specifications of ADM6996L-AA-T-1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 2
Pin or Ball
No.
61
59
60
62
66
74
100
101
102
73
68
78
77
72
67
Data Sheet
6th Port (MII) Interfaces (cont’d)
Name
TXD[1]
SettingP5GPSI
TXD3
TXD2
P4FX
XEN
SettingPHYAS0
RXD0
RXD1
RXD2
RXD3
RXDV
RXER
COL
CRS
RXCLK
TXCLK
Pin
Type
I/O
I/O
I/O
I/O
I
I/O
I/O
I
I
I
I
I
I
I
I
I
I
Buffer
Type
8mA
PD
8mA
PD
8mA
PD
8mA
PD
PD
8mA
PD
8mA
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
Function
MII Tx Data 1
Synchronous to the rising edge of TXCLK. These pins act
as MII TXD[1].
SettingP5GPSI
Port 5 GPSI Enable. At power-on-reset, latched as P5
GPSI Enable.“0” to disable port 5 GPSI (default), “1” to
enable port 5 GPSI.
MII Tx Data bits 3
MII Transmit Data bit 3~2Synchronous to the rising edge of
TXCLK. These pins act as MII TXD[3:2].
MII Tx Data bits 2
MII Transmit Data bit 3~2Synchronous to the rising edge of
TXCLK. These pins act as MII TXD[3:2].
Port4 FX/TX mode select
Internal pull down.
1
0
MII Transmit Enable /GPSI TXEN
Internal pull down.
SettingPHYAS0
Chip physical address for multiple chip applications on read
EEPROM data. Internal pull down.Power on reset value
PHYAS0 combines with PHYAS1PHYAS1 PHYAS00 0
Master(93C46)
MII port receive data 0 /GPSI RXD
This pin acts as MII RXD0. Synchronous to the rising edge
of RXCLK. Internal pull down.
MII port receive data 1
This pins act as MII RXD1. Synchronous to the rising edge
of RXCLK. Internal pull down.
MII port receive data 2
These pins act as MII RXD2. Synchronous to the rising
edge of RXCLK. Internal pull down.
MII port receive data 3
These pins act as MII RXD3. Synchronous to the rising
edge of RXCLK. Internal pull down.
MII receive data valid.
Internal pull down.
MII Port Receive Error.
Internal pull down.
MII Port Collision input /GPSI Collision Input
Internal pull down.
MII Port Carrier Sense /GPSI Carrier Sense
Internal pull down.
MII Port Receive Clock Input /GPSI RXCLK
MII Port Transmit clock Input /GPSI TXCLK
B
B
11
Port4 as FX port.,
Port4 as TX port.,
Interface Description
Rev. 1.13, 2005-11-22
ADM6996L/LX
Data Sheet