ADM6996L-AA-T-1 Lantiq, ADM6996L-AA-T-1 Datasheet - Page 16

• Manufacturer Part Number: ADM6996L-AA-T-1
• Manufacturer: Lantiq

Specifications of ADM6996L-AA-T-1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

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3.1
The ADM6996L/LX integrates five 100Base-X physical sub-layer (PHY), 100Base-TX physical medium dependent
(PMD) transceivers, five complete 10Base-T modules, a 6 port 10/100 switch controller and one 10/100 MII/GPSI
MAC and memory into a single chip for both 10Mbits/s, 100Mbits/s Ethernet switch operation. It also supports
100Base-FX operation through external fiber-optic transceivers. The device is capable of operating in either Full
Duplex mode or Half-Duplex mode in 10Mbits/s and 100Mbits/s. Operational modes can be selected by hardware
configuration pins, software settings of management registers, or determined by the on-chip auto negotiation logic.
The ADM6996L/LX consists of three major blocks:
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The interfaces used for communication between the PHY block and switch core is an MII interface.
An auto MDIX function is supported in this block. This function can be Enabled and Disabled by the hardware pin.
3.2
The 100Base-X section of the device implements the following functional blocks:
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The 100Base-X and 10Base-T sections share the following functional blocks:
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3.3
The ADM6996L/LX implements a 100Base-X compliant PCS and PMA and 100Base-TX compliant TP-PMD as
illustrated in Figure 2. Bypass options for each of the major functional blocks within the 100Base-X PCS provides
flexibility for various applications. 100Mbits/s PHY loop back is included for diagnostic purpose.
3.4
The 100Base-X receiver consists of functional blocks required to recover and condition the 125Mbits/s receive
data stream. The ADM6996L/LX implements the 100Base-X receiving state machine diagram as given in the
ANSI/IEEE Standard 802.3u, Clause 24. The 125Mbits/s receive data stream may originate from the on-chip
twisted-pair transceiver in a 100Base-TX application. Alternatively, the receive data stream may be generated by
an external optical receiver as in a 100Base-FX application.
The receiver block consists of the following functional sub-blocks:
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Data Sheet
10/100M PHY Block
Switch Controller Block
Built-in SSRAM
100Base-X physical coding sub-layer (PCS)
100Base-X physical medium attachment (PMA)
Twisted-pair transceiver (PMD)
Clock synthesizer module
MII Registers
IEEE 802.3u auto negotiation
A/D Converter
Adaptive Equalizer and timing recovery module
NRZI/NRZ and serial/parallel decoder
De-scrambler
Symbol alignment block
Symbol Decoder
Collision Detect Block
Carrier sense Block
Stream decoder block
Function Description
Functional Descriptions
10/100M PHY Block
100Base-X Module
100Base-X Receiver
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Function Description
Rev. 1.13, 2005-11-22
ADM6996L/LX
Data Sheet