ADM6996L-AA-T-1 Lantiq, ADM6996L-AA-T-1 Datasheet - Page 47

• Manufacturer Part Number: ADM6996L-AA-T-1
• Manufacturer: Lantiq

Specifications of ADM6996L-AA-T-1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 21
Mode
Interrupt low,
mask clearing
Interrupt enable
register
latch_on_reset
Read/write
self clearing
Table 22
Clock Short Name
4.2.1
Chip Identifier Register
ChipID
Chip Identifier Register
Field
ID
Ver
Port Status Register 0
PortStat_0
Port Status Register 0
Data Sheet
Register Access Types (cont’d)
Registers Clock DomainsRegisters Clock Domains
Serial Registers
Bits
31:4
3:0
Symbol Description HW
ilmk
ien
lor
rwsc
Differentiate the input signal (low-
>high) register cleared with written
mask
Enables the interrupt source for
interrupt generation
rw register, value is latched after first
clock cycle after reset
Register is used as input for the hw, the
register will be cleared due to a HW
mechanism.
Type
ro
ro
Description
Description
Chip Identifier Register
0000 7101
Version No
0000
H
Ver, Version No.
H
ID, Chip Identifier
Offset
Offset
00
01
47
H
H
Registers DescriptionSerial Register Map
Description SW
SW can read the register, with write mask
the register can be cleared
SW can read and write this register
Register is read and writable by SW
Writing to the register generates a strobe
signal for the HW (1 pdi clock cycle)
Register is read and writable by SW.
Rev. 1.13, 2005-11-22
ADM6996L/LX
Data Sheet
Reset Value
Reset Value
0000 0000
0000 0000
H
H