FAGD16556ECLBA Intel, FAGD16556ECLBA Datasheet - Page 11

• Manufacturer Part Number: FAGD16556ECLBA
• Manufacturer: Intel

Specifications of FAGD16556ECLBA

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Not Compliant

Lock Detect
Each PLL is equipped with a LVTTL lock
detect output that signals whether or not
the PLL is locked. A logic “1" indicates no
lock and a logic ”0" indicates in lock. The
pins LOCK1 and LOCK2 should be con-
nected to a 10 nF capacitance
20). The LVTTL output LOCK1A indi-
cates the state of the VCXO based PLL
and the LVTTL output LOCK2A indicates
the state of the on-chip VCO based PLL.
Figure 20.Lock detect
Jitter Transfer
The basic idea of the double PLL system
is to create a narrow bandwidth jitter
transfer performance of the system. The
jitter-transfer of the double PLL system is
shown on
Figure 21.The closed-loop transfer func-
The bandwidth of the VCXO based PLL
is denoted LBW1 and the bandwidth of
the VCO based PLL is denoted LBW2.
The VCXO PLL is locked to the incoming
clock (CKI, CKIN). Since the loop band-
width of the VCXO based PLL (LBW1)
can be chosen to a few kHz, jitter on the
incoming clock is suppressed above the
VCXO PLL loop bandwidth. The on-chip
high-speed VCO used for clock multipli-
cation tracks the VCXO through the sec-
ond PLL. This generates a very low-
noise high-speed clock. The loop band-
width of the VCO based PLL is made
Data Sheet Rev.: 23
0 dB
H(s)
Figure
tion of the double PLL system.
VEE
VEE
10 nF
10 nF
21.
LBW1
LOCK1
LOCK2
-20 dB/dec.
LBW2
(Figure
Frequency
-40 dB/dec.
wide (typ. 2 MHz) for suppression of the
intrinsic phase noise present in the VCO.
Jitter Generation
The overall jitter performance of the de-
vice is the sum of the jitter on the input
clock with respect to the jitter-transfer of
the device and the jitter generation of the
device itself. The choice of loop band-
widths and VCXO for the double PLL will
assure that the transponder system
meets the jitter requirements. The jitter
generation of the GD16557 is minimised
through a careful design and layout of
the device and a low-noise on-chip VCO.
Multi Bitrate Operation and
Gigabit Ethernet
Operation of the device transmitting
STM-1 (OC3), STM-4 (OC12) and
STM-16 (OC48) bit rates requires a
single VCXO with a centre frequency ac-
cording to Table 1 on
to achieve the line rate for Gigabit Ether-
net it is most likely necessary to add a
second VCXO (Due to the usual limited
tuning range of VCXOs). This is made
possible by adding two VCXO inputs in
parallel (XCK1, XCK1N and XCK2,
XCK2N) selectable by the signal
VCXOSEL. The concurrent use of two
VCXOs requires a slightly modified
loop-filter that will be determined during
prototype test. When using several
VCXOs it is important to consider the
possibility of crosstalk between the
VCXO clock signals. It is recommended
to disconnect the power supply for the
VCXO not in use.
Bit Order
The bits DI0..DI15 are multiplexed into a
serial stream with DI0 as the first bit
transmitted and DI15 as the last bit in a
16 bit frame.
GD16556/GD16557*
page
11. However,
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