FAGD16556ECLBA Intel, FAGD16556ECLBA Datasheet - Page 5

• Manufacturer Part Number: FAGD16556ECLBA
• Manufacturer: Intel

Specifications of FAGD16556ECLBA

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Not Compliant

The Receiver – GD16556
General
The GD16556 is an on-the-fly program-
mable multi-bitrate CDR and 1:16 de-
multiplexer with emphasis put on tran-
sponder applications. The device is ca-
pable of demultiplexing a serial bit
stream at 155 Mbit/s, 622 Mbit/s,
1.250 Gbit/s or 2.488 Mbit/s into 16 par-
allel low speed channels.
When operated in non-transponder appli-
cations the device meets all ITU-T /
Bellcore jitter specifications when used
with the recommended loop filter (Refer
to
dependent on the bit-rate in order to
achieve the jitter specifications. In this
case true on-the-fly multi-bitrate opera-
tion is not an option.
When operated in the transponder con-
figuration Figure 1 true multi-bitrate oper-
ation is made possible by a trade-off
between jitter-tolerance and jitter-transfer
in the receiver. By allowing an increase
in jitter-transfer the jitter tolerance is
achieved at any bitrate. The double-PLL
jitter clean-up system on the transmitter
“equalizes” this penalty on the transmit
side.
Figure 10.GD16556 - Block diagram
Data Sheet Rev.: 23
Figure
19). Note that the loop-filter is
CKREFAN
CKREFBN
MSEL1..2
RSEL1..2
CKREFA
CKREFB
DIREFN
DIREF
VCTL
DIN
DI
2
2
LIA
&
Clock Generator
/56, /60
/62, /64
/4, /16
/1, /2
Hence, the overall transponder system
will be well within the jitter specifications.
Select pins are LVTTL compatible. The
LVTTL inputs are internally pulled high
by default.
The device operates from a single 3.3 V
positive power-supply and the consump-
tion is 1.3 W (typ.).
Digital “Wrapping” Modes
The GD16556 is capable of receiving
data at increased bit rates if overhead
capability for system purposes is needed.
Table 1
straints on the reference clock and the
setting of the MSEL1, MSEL2 signals for
the transponder system shown on
1.
4
4
on
GD16556/GD16557*
Detect.
Phase
Bang
Bang
page 11
outlines the con-
F
V
Detect
PFD
Lock
Clock
Figure
&
&
Clock Generator Circuit
The clock generator circuit in the
GD16556 contains two independent di-
viders.
One divider (divide by 1 for STM-16/OC
48, divide by 2 for Gigabit Ethernet, di-
vide by 4 for STM-4/OC 12 and divide by
16 for STM-1/OC 3) generates the line
rate clock to the Bang-Bang phase de-
tector plus decision sampling gaate.
A second divider (56, 60, 62 and 64) di-
vides the VCO frequency to generate a
signal that is compared with the refer-
ence clock in the Phase Frequency De-
tector (PFD). This signal is also
forwarded to the transmitter GD16557
when operated in a transponder system.
The circuit topology allows for a straight-
forward increase in line rates by a frac-
tion. The simplest illustration is by
example.
DeMUX
CHAP
1:16
16
DO0..15
DO0N..15N
CKO
CKON
VDD
VDDL
VDDO
VDDP
VDDV
LOCK
VEE
VEEL
VEEP
VEEV
OUCHP
FCK
FCKN
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