SLXT970AQC.B11-831643 Cortina Systems Inc, SLXT970AQC.B11-831643 Datasheet - Page 28

• Manufacturer Part Number: SLXT970AQC.B11-831643
• Manufacturer: Cortina Systems Inc

Specifications of SLXT970AQC.B11-831643

• Number Of Receivers: 1
• Data Rate: 10/100Mbps
• Operating Supply Voltage (typ): 5V
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Mounting: Surface Mount
• Pin Count: 64
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Lead Free Status / RoHS Status: Not Compliant

Intel
2.3.2
2.3.2.1
2.3.2.2
28
®
LXT970A Dual-Speed Fast Ethernet Transceiver
Reference Clock Requirements
The LXT970A Transceiver requires a continuous, stable reference clock. There are two clock
modes, Master Clock Mode and Slave Clock Mode. Depending on the mode of operation, the clock
may be supplied at the crystal oscillator pins (XI, XO), or at the Transmit Clock pin (TX_CLK).
See
Master Clock Mode
The Master Clock mode is recommended in most Network Interface Cards (NICs) and switch
applications. In Master Clock mode the LXT970A Transceiver is the master clock source for data
transmission, and requires a 25 MHz reference signal at XI. The reference clock may be supplied
either from a crystal oscillator or from a digital clock circuit with the following specifications:
In Master Clock Mode, TX_CLK is an output and the LXT970A Transceiver automatically sets the
speed of TX_CLK to match line conditions. If the line is operating at 100 Mbps, TX_CLK will be
set to 25 MHz. If the line is operating at 10 Mbps, TX_CLK will be set to 2.5 MHz.
External Crystal
A crystal is typically used in NIC applications. If using a crystal oscillator, it should be
fundamental-mode and parallel-resonant, with a drive capacity of at least 7 pF. Attach between the
XI and XO pins. Add compensating capacitors between each leg and digital ground. The correct
value to use is the nominal drive capacity of the crystal minus 3 pF (input capacitance of the XI and
XO pins). One crystal can be used to drive two LXT970A Transceivers. Connect the XO pin of
only one 970 to one side of the crystal, and connect the other side to both XI pins. Calculate
compensation accordingly.
External Clock
An external 25 MHz clock source, rather than a crystal, is frequently used in switch applications.
When a clock is supplied to XI, XO is left open.
TX Clock Advance Mode
When operating in Master Clock mode under MDIO Control, the user can advance the transmit
clock relative to TXD<4:0> and TX_ER. When TX_CLK Advance is selected, the
LXT970A Transceiver clocks TXD data in on the falling edge of TX_CLK, instead of the rising
edge.
This mode provides an increase in timing margins of TXD, relative to TX_CLK. TX_CLK
Advance is enabled when bit 19.5 = 1.
Slave Clock Mode
The Slave Clock mode is typically used for repeater applications, where the LXT970A Transceiver
is not the master clock source for data transmissions. In Slave Clock Mode, a digital clock circuit
with TTL levels (V
•
•
•
Table 25 on page 48
A frequency of 25 MHz +/-100 ppm
40/60 duty cycle or better
CMOS voltage levels (V
OH
>2.4V) must supply the TX_CLK input. The frequency may be either 25
for input clock requirements.
OH
>3.2V).
Datasheet