1893BKILFT IDT, Integrated Device Technology Inc, 1893BKILFT Datasheet
1893BKILFT
Specifications of 1893BKILFT
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1893BKILFT Summary of contents
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... Auto-MDIX feature that automatically corrects crossover errors in plant wiring. The ICS1893BF incorporates Digital-Signal Processing (DSP) control in its Physical-Medium Dependent (PMD) sub layer result, it can transmit and receive data on unshielded twisted-pair (UTP) category 5 cables with attenuation in excess 100MHz. With this ICS-patented technology, the ICS1893BF can virtually eliminate errors from killer packets ...
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ICS1893BF Data Sheet - Release Section Chapter 1 Abbreviations and Acronyms ......................................................................................... 10 Chapter 2 Conventions and Nomenclature..................................................................................... 12 Chapter 3 Overview of the ICS1893BF............................................................................................. 14 3.1 100Base-TX Operation .......................................................................................... 15 3.2 10Base-T Operation ............................................................................................... 15 Chapter 4 Operating Modes ...
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ICS1893BF Data Sheet Rev Release Section 6.3 Functional Block: 100Base-X PCS and PMA Sublayers ........................................ 36 6.3.1 PCS Sublayer ........................................................................................................ 36 6.3.2 PMA Sublayer ........................................................................................................ 36 6.3.3 PCS/PMA Transmit Modules ................................................................................. 37 6.3.4 PCS/PMA Receive Modules .................................................................................. 37 ...
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... Auto-Negotiation Ability (bit 1.3) ............................................................................ 60 7.3.11 Link Status (bit 1.2) ................................................................................................ 60 7.3.12 Jabber Detect (bit 1.1) ........................................................................................... 61 7.3.13 Extended Capability (bit 1.0) .................................................................................. 61 7.4 Register 2: PHY Identifier Register ........................................................................ 62 ICS1893BF, Rev. E, 8/11/09 Table of Contents Title Copyright © 2009, IDT, Inc. All rights reserved. 4 Table of Contents Page ...
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... ICS1893BF Data Sheet Rev Release Section 7.5 Register 3: PHY Identifier Register ........................................................................ 63 7.5.1 OUI bits 19-24 (bits 3.15:10) .................................................................................. 63 7.5.2 Manufacturer's Model Number (bits 3.9:4) ............................................................. 63 7.5.3 Revision Number (bits 3.3:0) ................................................................................. 63 7.6 Register 4: Auto-Negotiation Register ................................................................... 65 7.6.1 Next Page (bit 4.15) ............................................................................................... 65 7.6.2 IEEE Reserved Bit (bit 4.14) .................................................................................. 66 7 ...
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... Register 16: Extended Control Register ................................................................ 76 7.11.1 Command Override Write Enable (bit 16.15) ......................................................... 77 7.11.2 ICS Reserved (bits 16.14:11) ................................................................................. 77 7.11.3 PHY Address (bits 16.10:6) ................................................................................... 77 7.11.4 Stream Cipher Scrambler Test Mode (bit 16.5) ..................................................... 77 7.11.5 ICS Reserved (bit 16.4) ......................................................................................... 77 7.11.6 NRZ/NRZI Encoding (bit 16.3) ............................................................................... 77 7.11.7 Invalid Error Code Test (bit 16 ...
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... Pin Diagram, Listings, and Descriptions ....................................................................... 90 8.1 ICS1893BF Pin Diagram ........................................................................................ 90 8.2 ICS1893BF Pin Descriptions ................................................................................. 91 8.2.1 Transformer Interface Pins ..................................................................................... 92 8.2.2 Multi-Function (Multiplexed) Pins: PHY Address and LED Pins ............................. 92 8.2.3 Configuration Pins................................................................................................... 96 8.2.4 MAC Interface Pins ................................................................................................. 97 8.2.5 Ground and Power Pins........................................................................................101 8.3 ICS1893BK Pin Diagram with MDIX Pinout (56L, 8x8 MLF2) ..............................102 8 ...
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... Jabber Timing .....................................................................................127 9.5.19 10Base-T: Normal Link Pulse Timing ..................................................................128 9.5.20 Auto-Negotiation Fast Link Pulse Timing .............................................................129 Chapter 10 Physical Dimensions of ICS1893BF Package........................................................... 130 Chapter 11 Ordering Information.................................................................................................... 132 ICS1893BF, Rev. E, 8/11/09 Table of Contents Title Copyright © 2009, IDT, Inc. All rights reserved. ...
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... Ground and Power Pins and related Tables 8-13 and 8-14. – Page 111. Industrial Temperature operating conditions added to Table 9-2. – Page 135. Figure 10-2 Quad Flat/No Lead Plastic Package physical dimensions added. – Page 136. Table 11-1 ICS1893BF ordering information revised to add new package options. ...
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ICS1893BF Data Sheet - Release Chapter 1 Abbreviations and Acronyms Table 1-1 lists and interprets the abbreviations and acronyms used throughout this data sheet. Table 1-1. Abbreviations and Acronyms Abbreviation / Acronym 4B/5B 4-Bit / 5-Bit Encoding/Decoding ANSI American National ...
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... Open Systems Interconnection OUI Organizationally Unique Identifier PCS Physical Coding sublayer PHY physical-layer device The ICS1893BF is a physical-layer device, also referred ‘PHY’ or ‘PHYceiver’. (The ICS1890 is also a physical-layer device.) PLL phase-locked loop PMA Physical Medium Attachment PMD Physical Medium Dependent ...
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ICS1893BF Data Sheet - Release Chapter 2 Conventions and Nomenclature Table 2-1 lists and explains the conventions and nomenclature used throughout this data sheet. Table 2-1. Conventions and Nomenclature Item Bits Code groups Colon (:) Numbers Pin (or signal) names ...
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ICS1893BF Data Sheet Rev Release Table 2-1. Conventions and Nomenclature (Continued) Item Signal references Symbols Terms: ‘set’, ‘active’, ‘asserted’, Terms: ‘cleared’, ‘de-asserted’, ‘inactive’ Terms: ‘twisted-pair receiver’ Terms: ‘twisted-pair transmitter’ ICS1893BF, Rev. E, 8/11/09 Convention / Nomenclature • When ...
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... It subsequently presents these nibbles to its MAC Interface. The ICS1893BF implements the OSI model’s physical layer, consisting of the following, as defined by the ISO/IEC 8802-3 standard: • ...
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ICS1893BF Data Sheet Rev Release 3.1 100Base-TX Operation During 100Base-TX data transmission, the ICS1893BF accepts packets from a MAC and inserts Start-of-Stream Delimiters (SSDs) and End-of-Stream Delimiters (ESDs) into the data stream. The ICS1893BF encapsulates each MAC frame, ...
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ICS1893BF Data Sheet - Release Chapter 4 Operating Modes Overview The ICS1893BF operating modes are typically controlled from software. The ICS1893BF register bits are accessible through a standard MII (Media Independent Interface) Serial Management Port. The ICS1893BF is configured to ...
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... Exits the power-down state 2. Latches the Serial Management Port Address of the ICS1893BF into the Extended Control Register, bits 16.10:6. [See Section 7.11.3, “PHY Address (bits 3. Enables all its internal modules and state machines 4. Sets all Management Register bits to their default values 5 ...
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ICS1893BF Data Sheet - Release 4.1.2 Specific Reset Operations This section discusses the following specific ways that the ICS1893BF can be reset: • Hardware reset (using the RESETn pin) • Power-on reset (applying power to the ICS1893BF) • Software reset ...
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... Address into the Extended Control Register. [For information on the Serial Management Port Address, see Section 7.11.3, “PHY Address (bits 3. The Control Register bit 0.15 does not represent the status of a hardware reset self-clearing bit that is used to initiate a software reset. During a hardware or power-on reset, Control Register bit 0.15 does not get set to logic one ...
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ICS1893BF Data Sheet - Release 4.3 Automatic Power-Saving Operations The ICS1893BF has power-saving features that automatically minimize its total power consumption while it is operating. Table 4-1 lists the ICS1893BF automatic power-saving features for the various modes. Table 4-1. Automatic ...
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... ISO/IEC 8802-3 standard. In the 100Base-TX mode, the ICS1893BF is a 100M translator between a MAC and the physical transmission medium. As such, the ICS1893BF has two interfaces, both of which are fully configurable: one to the MAC and one to the Link Segment. In 100Base-TX mode, the ICS1893BF provides the following functions: • ...
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... Two types of CAT 5 cables (straight and crossed) are available to achieve the correct connection. The Auto-MDI/MDIX feature automatically corrects for miss-wired installations by automatically swapping transmit and receive signal pairs at the PHY when no link results. Auto-MDI/MDIX is automatic, but may be disabled for test purposes using the AMDIX_EN pin or by writing MDIO register 19 Bits 9:8 in the MDIO register ...
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... ICS1893BF Data Sheet Rev Release Chapter 5 Interface Overviews The ICS1893BF MAC Interface is fully configurable, thereby allowing it to accommodate many different applications. This chapter includes overviews of the following MAC-to-PHY interfaces: • Section 5.1, “MII Data Interface” • Section 5.2, “Serial Management Interface” ...
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... The ICS1893BF’s MAC Interface is the Media Independent Interface (MII) operating at either 10 Mbps or 100 Mbps. The ICS1893BF MAC Interface is configured for the MII Data Interface mode, data is transferred between the PHY and the MAC as framed, 4-bit parallel nibbles. In addition, the interface also provides status and control signals to synchronize the transfers. ...
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... ICS1893BF. The ISO/IEC standard also specifies a frame structure and protocol for this interface as well as a set of Management Registers that provide the STA with access to a PHY such as the ICS1893BF. A Serial Management Interface is comprised of two signals: a bi-directional data pin (MDIO) along with an associated input pin for a clock (MDC) ...
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ICS1893BF Data Sheet - Release Figure 5-1. ICS1893BF Twisted Pair TP_AP 12 ICS1893BF TP_AN 13 Ideally, for these traces Z TP_BP 16 TP_BN 15 Ideally, for these traces Z ICS1893BF, Rev. E, 8/11/09 System Ground Plane 1:1 61.9Ω 1% Center ...
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ICS1893BF Data Sheet Rev Release 5.4 Clock Reference Interface The REF_IN pin provides the ICS1893BF Clock Reference Interface. The ICS1893BF requires a single clock reference with a frequency of 25 MHz ±50 parts per million. This accuracy is ...
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ICS1893BF Data Sheet - Release If a crystal is used as the clocking source, connect it to both the Ref_in (pin 47) and Ref_out (pin 46) pins of the ICS1893BF. A pair of bypass capacitors on either side of the ...
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... Adding 10KΩ resistors across the LEDs ensures the PHY address is fully defined during slow VDD power-ramp conditions. 6. PHY address 00 tri-states the MII interface. (Do not select PHY address 00 unless you want the MII tri-stated.) ICS1893BF, Rev. E, 8/11/09 Copyright © ...
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... This circuit decodes to PHY address = 1. Notes: 1. All LED pins must be set during reset. 2. Caution: PHY address 00 tri-states the MII interface. Don’t use PHY address 00. 3. For more reliable address capture during power-on reset, add a 10KΩ resistor across the LED. ...
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ICS1893BF Data Sheet Rev Release Chapter 6 Functional Blocks This chapter discusses the following ICS1893BF functional blocks. • Section 6.1, “Functional Block: Media Independent Interface” • Section 6.2, “Functional Block: Auto-Negotiation” • Section 6.3, “Functional Block: 100Base-X PCS ...
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... The Media Independent Interface (MII) consists of two primary components interface between a MAC (Media Access Control sublayer) and the PHY (that is, the ICS1893BF). This MAC-PHY part of the MII consists of three subcomponents synchronous Transmit interface that includes the following signals: ...
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... Auto-Negotiation General Process The Auto-Negotiation sublayer uses a physical signaling technique that is transparent at the packet level and all higher protocol levels. This technique builds on the link pulse mechanism employed in 10Base-T operations and is fully compliant with clause 28 of the ISO/IEC 8802-3 standard. ...
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ICS1893BF Data Sheet - Release 6. To indicate that the auto-negotiation process is complete, the ICS1893BF sets bits 1.5 and 17.4 high to logic one. After successful completion of the auto-negotiation process, the ICS1893BF Auto-Negotiation sublayer performs the following steps: ...
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ICS1893BF Data Sheet Rev Release 6.2.3 Auto-Negotiation: Remote Fault Signaling If the remote link partner detects a fault, the ICS1893BF reports the remotely detected fault to the STA by setting to logic one the Remote Fault Detected bit(s), ...
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... Assertion of the COL (collision detection) signal 6.3.2 PMA Sublayer The ICS1893BF 100Base-X PMA Sublayer consists of two interfaces: one to the Physical Coding sublayer and the other to the Physical Medium Dependent sublayer. Functionally, the PMA sublayer is responsible for the following: • Link Monitoring • ...
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... PMA Transmit Module The ICS1893BF PMA Transmit module accepts a serial bit stream from its PCS and converts the data into NRZI format. Subsequently, the PMA passes the NRZI bit stream to the Twisted-Pair Physical Medium Dependent (TP-PMD) sublayer. The ICS1893BF PMA Transmit module uses a digital PLL to synthesize a transmit clock from the Clock Reference Interface ...
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... NRZI Decoding The Receive module performs the NRZI decoding on the serial bit stream received from the Twisted-Pair Physical Medium Dependent (TP-PMD) sublayer. It converts the bit stream to a unipolar, positive, binary format that the PMA subsequently passes to the PCS. • Receive Clock Recovery The Receive Clock Recovery function consists of a phase-locked loop (PLL) that operates on the serial data stream received from the PMD sublayer ...
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... TP-PMD module performs stream-cipher scrambling/descrambling and MLT-3 encoding/decoding (3-level, multi-level transition) in compliance with the ANSI Standard X3.263: 199X FDDI TP-PMD as defined in the specification for 100Base-TX Twisted-Pair Physical Media Dependent (TP-PMD) Sublayer. The ICS1893BF’s TP-PMD also performs DC restoration (that is, baseline wander correction) and adaptive equalization on the received signals ...
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ICS1893BF Data Sheet - Release 6.4.2 100Base-TX Operation: MLT-3 Encoder/Decoder When operating in the 100Base-TX mode, the ICS1893BF TP-PMD sublayer employs an MLT-3 encoder and decoder. During data transmission, the TP-PMD encoder converts the NRZI bit stream received from the ...
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... The ICS1893BF interfaces with a medium through isolation transformers. The PHY requires two isolation transformers: one for its Twisted-Pair Transmitter and the other for its Twisted-Pair Receiver. These isolation transformers provide both physical isolation as well as the means for coupling a signal between the ICS1893BF and the medium for both 10Base-T and 100Base-TX operations. ...
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ICS1893BF Data Sheet - Release During 10Base-T data reception, a Manchester Decoder translates the serial bit stream obtained from the Twisted-Pair Receiver (MDI) into an NRZ bit stream. The Manchester Decoder then passes the data to the MAC Interface in ...
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... IDL to declare a link valid (that is, the reception of any data is sufficient). In 10Base-T mode, an ICS1893BF appends an IDL to the end of each packet during data transmission. The receiving PHY (the remote link partner) sees this IDL and removes it from the data stream. ICS1893BF, Rev. E, 8/11/09 Copyright © 2009, IDT, Inc. ...
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ICS1893BF Data Sheet - Release 6.5.7 10Base-T Operation: Carrier Detection The ICS1893BF has a 10Base-T Carrier Detection Function that establishes the state of its Carrier Sense signal (CRS), based upon the state of its Transmit and Receive state machines. These ...
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ICS1893BF Data Sheet Rev Release An ICS1893BF SQE Test Function is: • Enabled only when all the following conditions are true: – The ICS1893BF is in node mode. – The ICS1893BF is in half-duplex mode. – The ICS1893BF ...
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... The Serial Management Interface is a synchronous, bi-directional, two-wire, serial interface for the exchange of configuration, control, and status data between a PHY, such as an ICS1893BF, and an STA. All data transferred on an MDIO signal is synchronized by its MDC signal. The PHY and STA exchange data through a pre-defined register set. ...
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... The ability to process Management Frames that do not have a preamble is provided by the Management Frame Preamble Suppression bit, (bit 1.6 in the ICS1893BF’s Status Register). This is an ISO/IEC defined status bit that is intended to provide an indication of whether or not a PHY supports the MF Preamble Suppression feature. In order to maintain backward compatibility with the ICS1890, which did not support MF Preamble Suppression, the ICS1893BF MF Preamble Suppression bit is a Command Override Write bit which defaults to a logic zero ...
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... ICS1893BF Data Sheet - Release Upon receiving a valid STA transaction, during a power-on or hardware reset an ICS1893BF compares the PHYAD field included within the management frame with the value of its PHYAD bits stored in register 16. (For information on the PHYAD bits, see match its stored address bits. ...
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... Section 7.3, “Register 1: Status Register” • Section 7.4, “Register 2: PHY Identifier Register” • Section 7.5, “Register 3: PHY Identifier Register” • Section 7.6, “Register 4: Auto-Negotiation Register” • Section 7.7, “Register 5: Auto-Negotiation Link Partner Ability Register” • ...
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... Management Register Set Outline This section outlines the ICS1893BF Management Register set. Management Register Set that the ICS1893BF implements. Table 7-1. ISO/IEC-Specified Management Register Set Register Address 0 Control 1 Status 2,3 PHY Identifier 4 Auto-Negotiation Advertisement 5 Auto-Negotiation Link Partner Ability 6 Auto-Negotiation Expansion 7 Auto-Negotiation Next Page Transmit 8 ...
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... For some bits, the default value depends on the state (that is, the logic value particular pin at reset (that is, the logic value of a pin is latched at reset). An example of pins that have a default condition that depends on the state of the pin at reset are the PHY / LED pins (P0AC, P1CL, P2LI, P3TD, and P4RD) discussed in the following sections: Note: The ICS1893BF has a number of reserved bits throughout the Management Registers ...
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ICS1893BF Data Sheet - Release 7.1.4 Management Register Bit Special Functions This section discusses the types of special functions for the Management Register bits. 7.1.4.1 Latching High Bits The purpose of a latching high (LH) bit is to record an ...
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... IEEE reserved 0.1 IEEE reserved 0.0 IEEE reserved † Whenever the PHY address of • Is equal to 00000 (binary), the Isolate bit 0.10 is logic one. • Is not equal to 00000, the Isolate bit 0.10 is logic zero. ‡ As per the IEEE Std 802.3u, during any write operation to any bit in this register, the STA must write the default value to all Reserved bits ...
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ICS1893BF Data Sheet - Release 7.2.2 Loopback Enable (bit 0.14) This bit controls the Loopback mode for the ICS1893BF. Setting this bit to logic: • Zero disables the Loopback mode. • One enables the Loopback mode by disabling the Twisted-Pair ...
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... Management Interface continues to operate normally (that is, bit 0.10 does not affect the Management Interface). The default value for bit 0.10 depends upon the PHY address of • Is equal to 00000b, then the default value of bit 0.10 is logic one, and the ICS1893BF isolates itself from the MAC Interface. • ...
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ICS1893BF Data Sheet - Release 7.2.8 Duplex Mode (bit 0.8) This bit provides a means of controlling the ICS1893BF Duplex Mode. Its operation depends on several other functions, including the HW/SW input pin and the Auto-Negotiation Enable bit (bit 0.12). ...
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... No remote fault detected Remote fault detected N/A Always 1: PHY has Auto-Negotiation ability Link is invalid/down Link is valid/established No jabber condition Jabber condition detected N/A Always 1: PHY has extended capabilities Copyright © 2009, IDT, Inc. All rights reserved. 57 Chapter 7 Management Register Set Acronyms”. Ac- SF De- Hex ...
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ICS1893BF Data Sheet - Release 7.3.2 100Base-TX Full Duplex (bit 1.14) The STA reads this bit to learn if the ICS1893BF can support 100Base-TX, full-duplex operations. The ISO/IEC specification requires that the ICS1893BF must set bit 1.14 to logic: • ...
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ICS1893BF Data Sheet Rev Release 7.3.6 IEEE Reserved Bits (bits 1.10:7) The IEEE reserves these bits for future use. When an STA: • Reads a reserved bit, the ICS1893BF returns a logic zero. • Writes a reserved bit, ...
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ICS1893BF Data Sheet - Release 7.3.9 Remote Fault (bit 1.4) An STA reads bit 1.4 to determine if a Remote Fault exists. The ICS1893BF sets bit 1.4 based on the Remote Fault bit received from its remote link partner. The ...
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ICS1893BF Data Sheet Rev Release 7.3.12 Jabber Detect (bit 1.1) The purpose of this bit is to allow an STA to determine if the ICS1893BF detects a Jabber condition as defined in the ISO/IEC specification.The ICS1893BF Jabber Detection ...
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... Manufacturer’s PHY Revision Number, discussed in All of the bits in the two PHY Identifier Registers are Command Override Write bits. An STA can read them at any time without condition. However, an STA can modify these register bits only when the Command Register Override bit (bit 16.15) is enabled with a logic one. ...
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... Manufacturer’s PHY Revision Number All the bits in the two PHY Identifier Registers are Command Override Write bits. An STA can read them at any time without condition. However, An STA can modify these register bits only when the Command Register Override bit (bit 16.15) is enabled with a logic one. ...
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... ICS1893BF Data Sheet - Release Table 7-9. PHY Identifier Register (Register 3 [0x03]) Bit Definition 3.11 OUI bit 3.10 OUI bit 3.9 Manufacturer’s Model Number bit 5 3.8 Manufacturer’s Model Number bit 4 3.7 Manufacturer’s Model Number bit 3 3.6 Manufacturer’s Model Number bit 2 3.5 Manufacturer’ ...
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... ICS1893BF advertises (that is, exchanges) capability data with its remote link partner by using a pre-defined Link Code Word. The Link Code Word is embedded in the Fast Link Pulses exchanged between PHYs when the ICS1893BF has its Auto-Negotiation sublayer enabled. The value of the Link Control Word is established based on the value of the bits in this register. ...
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ICS1893BF Data Sheet - Release 7.6.2 IEEE Reserved Bit (bit 4.14) The ISO/IEC specification reserves this bit for future use. However, the ISO/IEC Standard also defines bit 4.14 as the Acknowledge bit. When this reserved bit is read by an ...
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ICS1893BF Data Sheet Rev Release 7.6.5 Technology Ability Field (bits 4.9:5) When its Auto-Negotiation sublayer is enabled, the ICS1893BF transmits its link capabilities to its remote link partner during the auto-negotiation process. The Technology Ability Field (TAF) bits ...
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ICS1893BF Data Sheet - Release 7.7 Register 5: Auto-Negotiation Link Partner Ability Register Table 7-12 lists the bits for the Auto-Negotiation Link Partner Ability Register. An STA uses this register to determine the capabilities being advertised by the remote link ...
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ICS1893BF Data Sheet Rev Release 7.7.2 Acknowledge (bit 5.14) The ISO/IEC specification defines bit 5.14 as the Acknowledge bit. When this bit is a: • Zero, it indicates that the remote link partner has not received the ICS1893BF ...
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ICS1893BF Data Sheet - Release 7.8 Register 6: Auto-Negotiation Expansion Register Table 7-13 lists the bits for the Auto-Negotiation Expansion Register, which indicates the status of the Auto-Negotiation process. Note: For an explanation of acronyms used in Table 7-13. Auto-Negotiation ...
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ICS1893BF Data Sheet Rev Release 7.8.2 Parallel Detection Fault (bit 6.4) The ICS1893BF sets this bit to a logic one if a parallel detection fault is encountered. A parallel detection fault occurs when the ICS1893BF cannot disseminate the ...
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ICS1893BF Data Sheet - Release 7.9 Register 7: Auto-Negotiation Next Page Transmit Register Table 7-14 lists the bits for the Auto-Negotiation Next Page Transmit Register, which establishes the contents of the Next Page Link Control Word that is transmitted during ...
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... ICS1893BF Data Sheet Rev Release 7.9.1 Next Page (bit 7.15) This bit is used by a PHY/STA to enable the transmission of Next Pages following the base Link Control Word as long as the remote link partner supports the Next Page features of Auto-Negotiation. This bit is used to establish the state of the Next Page (NP) bit of the Next Page Link Control Word (that is, the NP bit of the Next Page Link Control Word tracks this bit) ...
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ICS1893BF Data Sheet - Release 7.10 Register 8: Auto-Negotiation Next Page Link Partner Ability Register Table 7-15 lists the bits for the Auto-Negotiation Next Page Link Partner Ability Register, which establishes the contents of the Next Page Link Control Word ...
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... ICS1893BF Data Sheet Rev Release 7.10.1 Next Page (bit 8.15) This bit is used by a PHY/STA to enable the transmission of Next Pages following the base Link Control Word as long as the remote link partner supports the Next Page features of Auto-Negotiation. This bit is used to establish the state of the Next Page (NP) bit of the Next Page Link Control Word (that is, the NP bit of the Next Page Link Control word tracks this bit) ...
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... ICS reserved 16.10 PHY Address Bit 4 16.9 PHY Address Bit 3 16.8 PHY Address Bit 2 16.7 PHY Address Bit 1 16.6 PHY Address Bit 0 16.5 Stream Cipher Test Mode Normal operation 16.4 ICS reserved 16.3 NRZ/NRZI encoding 16.2 Transmit invalid codes 16.1 ICS reserved 16 ...
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... PHY Address (bits 16.10:6) These five bits hold the Serial Management Port Address of the ICS1893BF. During either a hardware reset or a power-on reset, the PHY address is read from the LED interface. (For information on the LED interface, see Section 5.5, “Status Interface” ...
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ICS1893BF Data Sheet - Release 7.11.7 Invalid Error Code Test (bit 16.2) The Invalid Error Code Test bit allows an STA to force the ICS1893BF to transmit symbols that are typically classified as invalid. The purpose of this test bit ...
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ICS1893BF Data Sheet Rev Release 7.12 Register 17: Quick Poll Detailed Status Register Table 7-18 lists the bits for the Quick-Poll Detailed Status Register. This register is a 16-bit read-only register used to provide an STA with detailed ...
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ICS1893BF Data Sheet - Release 7.12.1 Data Rate (bit 17.15) The Data Rate bit indicates the ‘selected technology’. If the ICS1893BF is in: • Hardware mode, the value of this bit is determined by the 10/100SEL input pin. • Software ...
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ICS1893BF Data Sheet Rev Release Note: An MDIO read of these bits provides a history of the greatest progress achieved by the auto-negotiation process. In addition, the MDIO read latches the present state of the Auto-Negotiation State Machine ...
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ICS1893BF Data Sheet - Release 7.12.6 False Carrier (bit 17.8) The False Carrier bit indicates to an STA the detection of a False Carrier by the ICS1893BF in 100Base mode. A False Carrier occurs when the ICS1893BF begins evaluating potential ...
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ICS1893BF Data Sheet Rev Release 7.12.9 Premature End (bit 17.5) The Premature End bit indicates to an STA the detection of two consecutive Idles in a 100Base data stream by the ICS1893BF. During reception of a valid packet, ...
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ICS1893BF Data Sheet - Release 7.13 Register 18: 10Base-T Operations Register The 10Base-T Operations Register provides an STA with the ability to monitor and control the ICS1893BF activity while the ICS1893BF is operating in 10Base-T mode. Note: 1. For an ...
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ICS1893BF Data Sheet Rev Release 7.13.2 Polarity Reversed (bit 18.14) The Polarity Reversed bit is used to inform an STA whether the ICS1893BF has detected that the signals on the Twisted-Pair Receive Pins (TP_RXP and TP_RXN) are reversed. ...
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ICS1893BF Data Sheet - Release 7.13.8 Link Loss Inhibit (bit 18.1) The Link Loss Inhibit bit allows an STA to prevent the ICS1893BF from dropping the link in 10Base-T mode. When an STA sets this bit to logic: • Zero, ...
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ICS1893BF Data Sheet Rev Release 7.14 Register 19: Extended Control Register 2 The Extended Control Register provides more refined control of the internal ICS1893BF operations. Note: 1. For an explanation of acronyms used in 2. During any write ...
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... MDI or MDIX configuration to match the cable plant by automatically swapping transmit and receive signal pairs at the PHY. Auto-MDI/MDIX is defaulted on but may be disabled for test purposes using either the AMDIX_EN (pin 10 writing (bits 19. 9:8). See Table 7-22 for AMDIX_EN (19,9) and MDI_MODE (19,8) operation ...
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ICS1893BF Data Sheet Rev Release Table 7-22. AMDIX_EN (Pin 10) and Control Bits 19. 9:8 AMDIX_EN (Pin 10) 1 Default Values: 1 Definitions: straight transmit = TP_AP & TP_AN receive = TP_BP & TP_BN cross transmit = TP_BP ...
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ICS1893BF Data Sheet - Release Chapter 8 Pin Diagram, Listings, and Descriptions 8.1 ICS1893BF Pin Diagram POAC 1 VSS 2 P1CL 3 P2LI 4 VSS 5 P3TD 6 VDD 7 P4RD 8 10/100 9 AMDIX_EN 10 VSS 11 TP_AP 12 ...
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... RXD0 RXDV RXCLK RXER TXCLK TXEN TXD0 TXD1 TXD2 TXD3 COL CRS Table 8-2. ICS 1893BF Multifunction Pins: PHY Address and LED Pins Signal Name P4RD P3TD P2LI P1CL P0AC Table 8-3. ICS1893BF Configuration Pins Signal Name 10/100 AMDIX_EN 100TCSR 10TCSR ICS1893BF, Rev ...
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... Multi-Function (Multiplexed) Pins: PHY Address and LED Pins Table 8-5 lists the pins for the multi-function group of pins (that is, the multiplexed PHY Address / LED pins). Note: 1. During either a power-on reset or a hardware reset, each multi-function configuration pin is an input that is sampled when the ICS1893BF exits the reset state. After sampling is complete, these pins are output pins that can drive status LEDs ...
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... This multi-function configuration pin is: – An input pin during either a power-on reset or a hardware reset. In this case, this pin configures the ICS1893BF PHY Address Bit 1. – An output pin following reset. In this case, this pin provides collision status for the ICS1893BF input pin: • ...
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... This multi-function configuration pin is: – An input pin during either a power-on reset or a hardware reset. In this case, this pin configures the address of the ICS1893BF PHY Address Bit 2. – An output pin following reset. In this case, this pin provides link status for the ICS1893BF. ...
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... Input or Output ICS1893BF, Rev. E, 8/11/09 Chapter 8 Pin Diagram, Listings, and Descriptions Pin Description PHY (Address Bit Receive Data LED. For more information on this pin, see • This multi-function configuration pin is: – An input pin during either a power-on reset or a hardware reset. In this case, this pin configures the ICS1893BF when either hardware mode or software mode. – ...
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ICS1893BF Data Sheet - Release 8.2.3 Configuration Pins Table 8-6 lists the configuration pins. Table 8-6. Configuration Pins Pin Pin Name Number 10/100SEL 9 10TCSR 19 100TCSR 20 REF_IN 47 REF_OUT 46 RESETn 23 ICS1893BF, Rev. E, 8/11/09 Pin Type ...
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ICS1893BF Data Sheet Rev Release 8.2.4 MAC Interface Pins This section lists pin descriptions for each of the following interfaces • Section 8.2.4.1, “MAC Interface Pins for Media Independent Interface” 8.2.4.1 MAC Interface Pins for Media Independent Interface ...
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ICS1893BF Data Sheet - Release Table 8-7. MAC Interface Pins: Media Independent Interface (MII) (Continued) Pin Pin Pin Name Number Type MDIO 26 Input/ Output RXCLK 34 Output ICS1893BF, Rev. E, 8/11/09 Chapter 8 Pin Diagram, Listings, and Descriptions Pin ...
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ICS1893BF Data Sheet Rev Release Table 8-7. MAC Interface Pins: Media Independent Interface (MII) (Continued) Pin Pin Pin Name Number Type RXD0 31 Output RXD1 30 RXD2 29 RXD3 28 RXDV 32 Output RXER 35 Output TXCLK 37 ...
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ICS1893BF Data Sheet - Release Table 8-7. MAC Interface Pins: Media Independent Interface (MII) (Continued) Pin Pin Pin Name Number Type TXD0 39 Input TXD1 40 TXD2 41 TXD3 42 TXEN 38 Input ICS1893BF, Rev. E, 8/11/09 Chapter 8 Pin ...
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ICS1893BF Data Sheet Rev Release 8.2.5 Ground and Power Pins Table 8-8. Ground and Power Pins Signal Name VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS ICS1893BF, Rev. E, 8/11/09 Chapter ...
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ICS1893BF Data Sheet - Release 8.3 ICS1893BK Pin Diagram with MDIX Pinout (56L, 8x8 MLF2) 10/100 1 AMDIX_EN 2 VSS 3 TP_AP 4 TP_AN 5 VDD 6 VDD 7 TP_BN 8 TP_BP 9 VSS 10 VDD_A 11 10TCSR 12 100TCSR ...
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... RXD1 RXD0 RXDV RXCLK RXER TXCLK TXEN TXD0 TXD1 TXD2 TXD3 COL CRS Table 8-10. ICS1893BK Multifunction Pins: PHY Address and LED Pins Signal Name P4RD P3TD P2LI P1CL P0AC Table 8-11. ICS1893BK Configuration Pins Signal Name 10/100 AMDIX_EN 10TCSR 100TCSR ICS1893BF, Rev ...
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... Twisted Pair Transformers connections are shown in Chapter 5. The transformer must be 1:1 ratio and symetrical for 10/100 MDI/MDIX applications since the transmit twisted pair and receive twisted pair are interchangeable. ICS1893 PHYs do not have power connections to the Transformer. All transformer power is supplied by the ICS1893BK. ...
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ICS1893BF Data Sheet Rev Release 8.3.3 Ground and Power Pins Table 8-13. ICS1893BK Ground and Power Pins Signal Name VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS ...
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ICS1893BF Data Sheet - Release Chapter 9 DC and AC Operating Conditions 9.1 Absolute Maximum Ratings Table 9-1 lists absolute maximum ratings. Stresses above these ratings can permanently damage the ICS1893BF. These ratings, which are standard values for IDT commercially ...
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ICS1893BF Data Sheet Rev Release 9.3 Recommended Component Values Table 9-3. Recommended Component Values for ICS1893BF Parameter Oscillator Frequency 10TCSR Resistor Value 100TCSR Resistor Value LED Resistor Value † There are two IEEE Std. 802.3 requirements that drive ...
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ICS1893BF Data Sheet - Release 9.4 DC Operating Characteristics This section lists the ICS1893BF DC operating characteristics. 9.4.1 DC Operating Characteristics for Supply Current Table 9-4 lists the DC operating characteristics for the supply current to the ICS1893BF under various ...
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ICS1893BF Data Sheet Rev Release 9.4.3 DC Operating Characteristics for REF_IN Table 9-6 lists the 3.3-V DC characteristics for the REF_IN pin. Note: The REF_IN input switch point is 50% of VDD. Table 9-6. 3.3-V DC Operating Characteristics ...
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ICS1893BF Data Sheet - Release 9.5 Timing Diagrams 9.5.1 Timing for Clock Reference In (REF_IN) Pin Table 9-8 lists the significant time periods for signals on the clock reference in (REF_IN) pin. shows the timing diagram for the time periods. ...
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ICS1893BF Data Sheet Rev Release 9.5.2 Timing for Transmit Clock (TXCLK) Pins Table 9-9 lists the significant time periods for signals on the Transmit Clock (TXCLK) pins for the various interfaces. Figure 9-3 shows the timing diagram for ...
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ICS1893BF Data Sheet - Release 9.5.3 Timing for Receive Clock (RXCLK) Pins Table 9-10 lists the significant time periods for signals on the Receive Clock (RXCLK) pins for the various interfaces. Figure 9-4 shows the timing diagram for the time ...
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ICS1893BF Data Sheet Rev Release 9.5.4 100M MII: Synchronous Transmit Timing Table 9-11 lists the significant time periods for the 100M MII Interface synchronous transmit timing. The time periods consist of timings of signals on the following pins: ...
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ICS1893BF Data Sheet - Release 9.5.5 10M MII: Synchronous Transmit Timing Table 9-12 lists the significant time periods for the 10M MII synchronous transmit timing. The time periods consist of timings of signals on the following pins: • TXCLK • ...
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ICS1893BF Data Sheet Rev Release 9.5.6 100M/MII Media Independent Interface: Synchronous Receive Timing Table 9-13 lists the significant time periods for the MII / 100M Stream Interface synchronous receive timing. The time periods consist of timings of signals ...
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ICS1893BF Data Sheet - Release 9.5.7 MII Management Interface Timing Table 9-14 lists the significant time periods for the MII Management Interface timing (which consists of timings of signals on the MDC and MDIO pins). Table 9-14. MII Management Interface ...
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ICS1893BF Data Sheet Rev Release 9.5.8 10M Media Independent Interface: Receive Latency Table 9-15 lists the significant time periods for the 10M MII timing. The time periods consist of timings of signals on the following pins: • TP_RX ...
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ICS1893BF Data Sheet - Release 9.5.9 10M Media Independent Interface: Transmit Latency Table 9-16 lists the significant time periods for the 10M MII transmit latency. The time periods consist of timings of signals on the following pins: • TXEN • ...
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ICS1893BF Data Sheet Rev Release 9.5.10 100M / MII Media Independent Interface: Transmit Latency Table 9-17 lists the significant time periods for the MII / 100 Stream Interface transmit latency. The time periods consist of timings of signals ...
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ICS1893BF Data Sheet - Release 9.5.11 100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) Table 9-18 lists the significant time periods for the 100M MII carrier assertion/de-assertion during half-duplex transmission. The time periods consist of timings of signals on the following pins: ...
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ICS1893BF Data Sheet Rev Release 9.5.12 10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) Table 9-19 lists the significant time periods for the 10M MII carrier assertion/de-assertion during half-duplex transmission. The time periods consist of timings of signals on the ...
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ICS1893BF Data Sheet - Release 9.5.13 100M MII Media Independent Interface: Receive Latency Table 9-20 lists the significant time periods for the 100M MII / 100M Stream Interface receive latency. The time periods consist of timings of signals on the ...
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ICS1893BF Data Sheet Rev Release 9.5.14 100M Media Independent Interface: Input-to-Carrier Assertion/De-Assertion Table 9-21 lists the significant time periods for the 100M MDI input-to-carrier assertion/de-assertion. The time periods consist of timings of signals on the following pins: • ...
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ICS1893BF Data Sheet - Release 9.5.15 Reset: Power-On Reset Table 9-22 lists the significant time periods for the power-on reset. The time periods consist of timings of signals on the following pins: • VDD • TXCLK Figure 9-16 shows the ...
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ICS1893BF Data Sheet Rev Release 9.5.16 Reset: Hardware Reset and Power-Down Table 9-23 lists the significant time periods for the hardware reset and power-down reset. The time periods consist of timings of signals on the following pins: • ...
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ICS1893BF Data Sheet - Release 9.5.17 10Base-T: Heartbeat Timing (SQE) Table 9-24 lists the significant time periods for the 10Base-T heartbeat (that is, the Signal Quality Error). The time periods consist of timings of signals on the following pins: • ...
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ICS1893BF Data Sheet Rev Release 9.5.18 10Base-T: Jabber Timing Table 9-25 lists the significant time periods for the 10Base-T jabber. The time periods consist of timings of signals on the following pins: • TXEN • TP_TX (that is, ...
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ICS1893BF Data Sheet - Release 9.5.19 10Base-T: Normal Link Pulse Timing Table 9-26 lists the significant time periods for the 10Base-T Normal Link Pulse (which consists of timings of signals on the TP_TXP pins). Table 9-26. 10Base-T Normal Link Pulse ...
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ICS1893BF Data Sheet Rev Release 9.5.20 Auto-Negotiation Fast Link Pulse Timing Table 9-27 lists the significant time periods for the ICS1893BF Auto-Negotiation Fast Link Pulse. The time periods consist of timings of signals on the following pins: • ...
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... ICS1893BF Data Sheet - Release Chapter 10 Physical Dimensions of ICS1893BF Package Figure 10-1. ICS1893BF 300 mil SSOP Physical Dimensions ICS1893BF, Rev. E, 8/11/09 Chapter 10 Physical Dimensions of ICS1893BF Copyright © 2009, IDT, Inc. All rights reserved. 130 August, 2009 ...
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... ICS1893BF Data Sheet Rev Release Figure 10-2. ICS1893BK Thermally Enhanced, Very Thin, Fine Pitch, Quad Flat / No Lead Plastic Package ICS1893BF, Rev. E, 8/11/09 Chapter 10 Physical Dimensions of ICS1893BF Copyright © 2009, IDT, Inc. All rights reserved. 131 August, 2009 ...
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... ICS1893BFLFT ICS1893BFI* ICS1893BFILF ICS1893BFIT* ICS1893BFILFT ICS1893BK* ICS1893BKLF ICS1893BKT* ICS1893BKLFT ICS1893BKI* ICS1893BKILF ICS1893BKIT* ICS1893BKILFT ICS1893BF, Rev. E, 8/11/09 Marking 1893BF 48-Lead 300-mil SSOP 1893BFLF 48-Lead SSOP Lead/Pb-Free 1893BF 48-Lead 300-mil SSOP, Tape and Reel 1893BFLF 48-Lead SSOP Lead/Pb-Free, Tape and Reel 1893BFI 48-Lead 300-mil SSOP ...
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ICS1893BF Data Sheet Rev Release 11.1 Marking Diagram Notes: 1. Line 3: ###### = Lot number. 2. Line 4: YYWW = Date code. 3. Line 5: Origin ICS1893BF, Rev. E, 8/11/09 Copyright © 2009, IDT, Inc. All rights ...
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ICS1893BF Data Sheet - Release Integrated Device Technology, Inc. Web Site: ICS1893BF, Rev. E, 8/11/09 http://www.idt.com Copyright © 2009, IDT, Inc. All rights reserved. 134 Chapter 11 Ordering Information August, 2009 ...
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ICS1893BF Data Sheet Rev Release ICS1893BF, Rev. E, 8/11/09 Copyright © 2009, IDT, Inc. All rights reserved. 135 Chapter 11 Ordering Information August, 2009 ...
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ICS1893BF Data Sheet - Release ICS1893BF, Rev. E, 8/11/09 Copyright © 2009, IDT, Inc. All rights reserved. 136 Chapter 11 Ordering Information August, 2009 ...
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ICS1893BF Data Sheet Rev Release ICS1893BF, Rev. E, 8/11/09 Copyright © 2009, IDT, Inc. All rights reserved. 137 Chapter 11 Ordering Information August, 2009 ...
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ICS1893BF Data Sheet - Release ICS1893BF, Rev. E, 8/11/09 Copyright © 2009, IDT, Inc. All rights reserved. 138 Chapter 11 Ordering Information August, 2009 ...