IDT1893CFLFT IDT, Integrated Device Technology Inc, IDT1893CFLFT Datasheet
IDT1893CFLFT
Specifications of IDT1893CFLFT
Related parts for IDT1893CFLFT
IDT1893CFLFT Summary of contents
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... Auto-MDIX feature that automatically corrects crossover errors in plant wiring. The ICS1893CF incorporates Digital-Signal Processing (DSP) control in its Physical-Medium Dependent (PMD) sub layer result, it can transmit and receive data on unshielded twisted-pair (UTP) category 5 cables with attenuation in excess 100MHz. With this ICS-patented technology, the ICS1893CF can virtually eliminate errors from killer packets ...
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ICS1893CF Data Sheet - Release Revision History • Initial preliminary release of this document, Rev A, dated July 10, 2006. • Rev B – remove all references to ICS1893CK; removed package drawing and ordering info. • Rev C – added ...
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ICS1893CF Data Sheet Rev Release Chapter 1 Abbreviations and Acronyms Table 1-1 lists and interprets the abbreviations and acronyms used throughout this data sheet. Table 1-1. Abbreviations and Acronyms Abbreviation / Acronym 4B/5B 4-Bit / 5-Bit Encoding/Decoding ANSI ...
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... Open Systems Interconnection OUI Organizationally Unique Identifier PCS Physical Coding sublayer PHY physical-layer device The ICS1893CF is a physical-layer device, also referred ‘PHY’ or ‘PHYceiver’. (The ICS1890 is also a physical-layer device.) PLL phase-locked loop PMA Physical Medium Attachment PMD Physical Medium Dependent ...
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ICS1893CF Data Sheet Rev Release Chapter 2 Conventions and Nomenclature Table 2-1 lists and explains the conventions and nomenclature used throughout this data sheet. Table 2-1. Conventions and Nomenclature Item Bits Code groups Colon (:) Numbers Pin (or ...
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ICS1893CF Data Sheet - Release Table 2-1. Conventions and Nomenclature (Continued) Item Signal references Symbols Terms: ‘set’, ‘active’, ‘asserted’, Terms: ‘cleared’, ‘de-asserted’, ‘inactive’ Terms: ‘twisted-pair receiver’ Terms: ‘twisted-pair transmitter’ ICS1893CF, Rev. J, 08/11/09 Convention / Nomenclature • When referring to ...
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... It subsequently presents these nibbles to its MAC Interface. The ICS1893CF implements the OSI model’s physical layer, consisting of the following, as defined by the ISO/IEC 8802-3 standard: • ...
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ICS1893CF Data Sheet - Release 3.1 100Base-TX Operation During 100Base-TX data transmission, the ICS1893CF accepts packets from a MAC and inserts Start-of-Stream Delimiters (SSDs) and End-of-Stream Delimiters (ESDs) into the data stream. The ICS1893CF encapsulates each MAC frame, including the ...
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ICS1893CF Data Sheet Rev Release Chapter 4 Operating Modes Overview The ICS1893CF operating modes are typically controlled from software. The ICS1893CF register bits are accessible through a standard MII (Media Independent Interface) Serial Management Port. The ICS1893CF is ...
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... Exits the power-down state 2. Latches the Serial Management Port Address of the ICS1893CF into the Extended Control Register, bits 16.10:6. [See Section 7.11.3, “PHY Address (bits 3. Enables all its internal modules and state machines 4. Sets all Management Register bits to their default values 5 ...
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ICS1893CF Data Sheet Rev Release 4.1.2 Specific Reset Operations This section discusses the following specific ways that the ICS1893CF can be reset: • Hardware reset (using the RESETn pin) • Power-on reset (applying power to the ICS1893CF) • ...
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... Address into the Extended Control Register. [For information on the Serial Management Port Address, see Section 7.11.3, “PHY Address (bits 3. The Control Register bit 0.15 does not represent the status of a hardware reset self-clearing bit that is used to initiate a software reset. During a hardware or power-on reset, Control Register bit 0.15 does not get set to logic one ...
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ICS1893CF Data Sheet Rev Release 4.3 Automatic Power-Saving Operations The ICS1893CF has power-saving features that automatically minimize its total power consumption while it is operating. Table 4-1 lists the ICS1893CF automatic power-saving features for the various modes. Table ...
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... ISO/IEC 8802-3 standard. In the 100Base-TX mode, the ICS1893CF is a 100M translator between a MAC and the physical transmission medium. As such, the ICS1893CF has two interfaces, both of which are fully configurable: one to the MAC and one to the Link Segment. In 100Base-TX mode, the ICS1893CF provides the following functions: • ...
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... Two types of CAT 5 cables (straight and crossed) are available to achieve the correct connection. The Auto-MDI/MDIX feature automatically corrects for miss-wired installations by automatically swapping transmit and receive signal pairs at the PHY when no link results. Auto-MDI/MDIX is automatic, but may be disabled for test purposes using the AMDIX_EN pin or by writing MDIO register 19 Bits 9:8 in the MDIO register ...
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... ICS1893CF Data Sheet - Release Chapter 5 Interface Overviews The ICS1893CF MAC Interface is fully configurable, thereby allowing it to accommodate many different applications. This chapter includes overviews of the following MAC-to-PHY interfaces: • Section 5.1, “MII Data Interface” • Section 5.2, “Serial Management Interface” ...
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... The ICS1893CF’s MAC Interface is the Media Independent Interface (MII) operating at either 10 Mbps or 100 Mbps. The ICS1893CF MAC Interface is configured for the MII Data Interface mode, data is transferred between the PHY and the MAC as framed, 4-bit parallel nibbles. In addition, the interface also provides status and control signals to synchronize the transfers. ...
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... ICS1893CF. The ISO/IEC standard also specifies a frame structure and protocol for this interface as well as a set of Management Registers that provide the STA with access to a PHY such as the ICS1893CF. A Serial Management Interface is comprised of two signals: a bi-directional data pin (MDIO) along with an associated input pin for a clock (MDC) ...
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ICS1893CF Data Sheet Rev Release Figure 5-1. ICS1893CF Twisted Pair * TP_AP 12 ICS1893CF TP_AN 13 Ideally, for these traces Z TP_BP 16 TP_BN 15 Ideally, for these traces Z * For backward compatibility, refer to the the ...
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ICS1893CF Data Sheet - Release 5.4 Clock Reference Interface The REF_IN pin provides the ICS1893CF Clock Reference Interface. The ICS1893CF requires a single clock reference with a frequency of 25 MHz ±50 parts per million. This accuracy is necessary to ...
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ICS1893CF Data Sheet Rev Release If a crystal is used as the clocking source, connect it to both the Ref_in (pin 47) and Ref_out (pin 46) pins of the ICS1893CF. A pair of bypass capacitors on either side ...
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... Adding 10KΩ resistors across the LEDs ensures the PHY address is fully defined during slow VDD power-ramp conditions. 6. PHY address 00 tri-states the MII interface. (Do not select PHY address 00 unless you want the MII tri-stated.) ICS1893CF, Rev. J, 08/11/09 Copyright © ...
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... This circuit decodes to PHY address = 1. Notes: 1. All LED pins must be set during reset. 2. Caution: PHY address 00 tri-states the MII interface. Don’t use PHY address 00. 3. For more reliable address capture during power-on reset, add a 10KΩ resistor across the LED. ...
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ICS1893CF Data Sheet - Release Chapter 6 Functional Blocks This chapter discusses the following ICS1893CF functional blocks. • Section 6.1, “Functional Block: Media Independent Interface” • Section 6.2, “Functional Block: Auto-Negotiation” • Section 6.3, “Functional Block: 100Base-X PCS and PMA ...
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... The Media Independent Interface (MII) consists of two primary components interface between a MAC (Media Access Control sublayer) and the PHY (that is, the ICS1893CF). This MAC-PHY part of the MII consists of three subcomponents synchronous Transmit interface that includes the following signals: ...
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... Auto-Negotiation General Process The Auto-Negotiation sublayer uses a physical signaling technique that is transparent at the packet level and all higher protocol levels. This technique builds on the link pulse mechanism employed in 10Base-T operations and is fully compliant with clause 28 of the ISO/IEC 8802-3 standard. ...
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ICS1893CF Data Sheet Rev Release 6. To indicate that the auto-negotiation process is complete, the ICS1893CF sets bits 1.5 and 17.4 high to logic one. After successful completion of the auto-negotiation process, the ICS1893CF Auto-Negotiation sublayer performs the ...
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ICS1893CF Data Sheet - Release 6.2.3 Auto-Negotiation: Remote Fault Signaling If the remote link partner detects a fault, the ICS1893CF reports the remotely detected fault to the STA by setting to logic one the Remote Fault Detected bit(s), 1.4, 5.13, ...
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... Assertion of the COL (collision detection) signal 6.3.2 PMA Sublayer The ICS1893CF 100Base-X PMA Sublayer consists of two interfaces: one to the Physical Coding sublayer and the other to the Physical Medium Dependent sublayer. Functionally, the PMA sublayer is responsible for the following: • Link Monitoring • ...
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... PMA Transmit Module The ICS1893CF PMA Transmit module accepts a serial bit stream from its PCS and converts the data into NRZI format. Subsequently, the PMA passes the NRZI bit stream to the Twisted-Pair Physical Medium Dependent (TP-PMD) sublayer. The ICS1893CF PMA Transmit module uses a digital PLL to synthesize a transmit clock from the Clock Reference Interface ...
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... NRZI Decoding The Receive module performs the NRZI decoding on the serial bit stream received from the Twisted-Pair Physical Medium Dependent (TP-PMD) sublayer. It converts the bit stream to a unipolar, positive, binary format that the PMA subsequently passes to the PCS. • Receive Clock Recovery The Receive Clock Recovery function consists of a phase-locked loop (PLL) that operates on the serial data stream received from the PMD sublayer ...
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... TP-PMD module performs stream-cipher scrambling/descrambling and MLT-3 encoding/decoding (3-level, multi-level transition) in compliance with the ANSI Standard X3.263: 199X FDDI TP-PMD as defined in the specification for 100Base-TX Twisted-Pair Physical Media Dependent (TP-PMD) Sublayer. The ICS1893CF’s TP-PMD also performs DC restoration (that is, baseline wander correction) and adaptive equalization on the received signals ...
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ICS1893CF Data Sheet Rev Release 6.4.2 100Base-TX Operation: MLT-3 Encoder/Decoder When operating in the 100Base-TX mode, the ICS1893CF TP-PMD sublayer employs an MLT-3 encoder and decoder. During data transmission, the TP-PMD encoder converts the NRZI bit stream received ...
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... The ICS1893CF interfaces with a medium through isolation transformers. The PHY requires two isolation transformers: one for its Twisted-Pair Transmitter and the other for its Twisted-Pair Receiver. These isolation transformers provide both physical isolation as well as the means for coupling a signal between the ICS1893CF and the medium for both 10Base-T and 100Base-TX operations. ...
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ICS1893CF Data Sheet Rev Release During 10Base-T data reception, a Manchester Decoder translates the serial bit stream obtained from the Twisted-Pair Receiver (MDI) into an NRZ bit stream. The Manchester Decoder then passes the data to the MAC ...
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... IDL to declare a link valid (that is, the reception of any data is sufficient). In 10Base-T mode, an ICS1893CF appends an IDL to the end of each packet during data transmission. The receiving PHY (the remote link partner) sees this IDL and removes it from the data stream. ICS1893CF, Rev. J, 08/11/09 Copyright © 2009, Integrated Device Technology, Inc. ...
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ICS1893CF Data Sheet Rev Release 6.5.7 10Base-T Operation: Carrier Detection The ICS1893CF has a 10Base-T Carrier Detection Function that establishes the state of its Carrier Sense signal (CRS), based upon the state of its Transmit and Receive state ...
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ICS1893CF Data Sheet - Release An ICS1893CF SQE Test Function is: • Enabled only when all the following conditions are true: – The ICS1893CF is in node mode. – The ICS1893CF is in half-duplex mode. – The ICS1893CF has a ...
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... The Serial Management Interface is a synchronous, bi-directional, two-wire, serial interface for the exchange of configuration, control, and status data between a PHY, such as an ICS1893CF, and an STA. All data transferred on an MDIO signal is synchronized by its MDC signal. The PHY and STA exchange data through a pre-defined register set. ...
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... The ability to process Management Frames that do not have a preamble is provided by the Management Frame Preamble Suppression bit, (bit 1.6 in the ICS1893CF’s Status Register). This is an ISO/IEC defined status bit that is intended to provide an indication of whether or not a PHY supports the MF Preamble Suppression feature. In order to maintain backward compatibility with the ICS1890, which did not support MF Preamble Suppression, the ICS1893CF MF Preamble Suppression bit is a Command Override Write bit which defaults to a logic zero ...
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... ICS1893CF Data Sheet Rev Release Upon receiving a valid STA transaction, during a power-on or hardware reset an ICS1893CF compares the PHYAD field included within the management frame with the value of its PHYAD bits stored in register 16. (For information on the PHYAD bits, see match its stored address bits. ...
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... Section 7.3, “Register 1: Status Register” • Section 7.4, “Register 2: PHY Identifier Register” • Section 7.5, “Register 3: PHY Identifier Register” • Section 7.6, “Register 4: Auto-Negotiation Register” • Section 7.7, “Register 5: Auto-Negotiation Link Partner Ability Register” • ...
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... Management Register Set Outline This section outlines the ICS1893CF Management Register set. Management Register Set that the ICS1893CF implements. Table 7-1. ISO/IEC-Specified Management Register Set Register Address 0 Control 1 Status 2,3 PHY Identifier 4 Auto-Negotiation Advertisement 5 Auto-Negotiation Link Partner Ability 6 Auto-Negotiation Expansion 7 Auto-Negotiation Next Page Transmit 8 ...
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... For some bits, the default value depends on the state (that is, the logic value particular pin at reset (that is, the logic value of a pin is latched at reset). An example of pins that have a default condition that depends on the state of the pin at reset are the PHY / LED pins (P0AC, P1CL, P2LI, P3TD, and P4RD) discussed in the following sections: Note: The ICS1893CF has a number of reserved bits throughout the Management Registers ...
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ICS1893CF Data Sheet Rev Release 7.1.4 Management Register Bit Special Functions This section discusses the types of special functions for the Management Register bits. 7.1.4.1 Latching High Bits The purpose of a latching high (LH) bit is to ...
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... IEEE reserved 0.1 IEEE reserved 0.0 IEEE reserved † Whenever the PHY address of • Is equal to 00000 (binary), the Isolate bit 0.10 is logic one. • Is not equal to 00000, the Isolate bit 0.10 is logic zero. ‡ As per the IEEE Std 802.3u, during any write operation to any bit in this register, the STA must write the default value to all Reserved bits ...
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ICS1893CF Data Sheet Rev Release 7.2.2 Loopback Enable (bit 0.14) This bit controls the Loopback mode for the ICS1893CF. Setting this bit to logic: • Zero disables the Loopback mode. • One enables the Loopback mode by disabling ...
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... Management Interface continues to operate normally (that is, bit 0.10 does not affect the Management Interface). The default value for bit 0.10 depends upon the PHY address of • Is equal to 00000b, then the default value of bit 0.10 is logic one, and the ICS1893CF isolates itself from the MAC Interface. • ...
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ICS1893CF Data Sheet Rev Release 7.2.8 Duplex Mode (bit 0.8) This bit provides a means of controlling the ICS1893CF Duplex Mode. Its operation depends on several other functions, including the HW/SW input pin and the Auto-Negotiation Enable bit ...
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... Always 1: PHY has Auto-Negotiation ability Link is invalid/down Link is valid/established No jabber condition Jabber condition detected N/A Always 1: PHY has extended capabilities Copyright © 2009, Integrated Device Technology, Inc. All rights reserved. 50 Chapter 7 Management Register Set Chapter 1, “Abbreviations and Acronyms”. When Bit = 1 ...
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ICS1893CF Data Sheet Rev Release 7.3.2 100Base-TX Full Duplex (bit 1.14) The STA reads this bit to learn if the ICS1893CF can support 100Base-TX, full-duplex operations. The ISO/IEC specification requires that the ICS1893CF must set bit 1.14 to ...
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ICS1893CF Data Sheet - Release 7.3.6 IEEE Reserved Bits (bits 1.10:7) The IEEE reserves these bits for future use. When an STA: • Reads a reserved bit, the ICS1893CF returns a logic zero. • Writes a reserved bit, the STA ...
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ICS1893CF Data Sheet Rev Release 7.3.9 Remote Fault (bit 1.4) An STA reads bit 1.4 to determine if a Remote Fault exists. The ICS1893CF sets bit 1.4 based on the Remote Fault bit received from its remote link ...
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ICS1893CF Data Sheet - Release 7.3.12 Jabber Detect (bit 1.1) The purpose of this bit is to allow an STA to determine if the ICS1893CF detects a Jabber condition as defined in the ISO/IEC specification.The ICS1893CF Jabber Detection function is ...
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... Manufacturer’s PHY Revision Number, discussed in All of the bits in the two PHY Identifier Registers are Command Override Write bits. An STA can read them at any time without condition. However, an STA can modify these register bits only when the Command Register Override bit (bit 16.15) is enabled with a logic one. ...
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... Manufacturer’s PHY Revision Number All the bits in the two PHY Identifier Registers are Command Override Write bits. An STA can read them at any time without condition. However, An STA can modify these register bits only when the Command Register Override bit (bit 16.15) is enabled with a logic one. ...
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... ICS1893CF Data Sheet Rev Release Table 7-9. PHY Identifier Register (Register 3 [0x03]) Bit Definition 3.11 OUI bit 3.10 OUI bit 3.9 Manufacturer’s Model Number bit 5 3.8 Manufacturer’s Model Number bit 4 3.7 Manufacturer’s Model Number bit 3 3.6 Manufacturer’s Model Number bit 2 3.5 Manufacturer’ ...
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... ICS1893CF advertises (that is, exchanges) capability data with its remote link partner by using a pre-defined Link Code Word. The Link Code Word is embedded in the Fast Link Pulses exchanged between PHYs when the ICS1893CF has its Auto-Negotiation sublayer enabled. The value of the Link Control Word is established based on the value of the bits in this register. ...
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ICS1893CF Data Sheet Rev Release 7.6.2 IEEE Reserved Bit (bit 4.14) The ISO/IEC specification reserves this bit for future use. However, the ISO/IEC Standard also defines bit 4.14 as the Acknowledge bit. When this reserved bit is read ...
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ICS1893CF Data Sheet - Release 7.6.5 Technology Ability Field (bits 4.9:5) When its Auto-Negotiation sublayer is enabled, the ICS1893CF transmits its link capabilities to its remote link partner during the auto-negotiation process. The Technology Ability Field (TAF) bits 4.12:5 determine ...
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ICS1893CF Data Sheet Rev Release 7.7 Register 5: Auto-Negotiation Link Partner Ability Register Table 7-12 lists the bits for the Auto-Negotiation Link Partner Ability Register. An STA uses this register to determine the capabilities being advertised by the ...
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ICS1893CF Data Sheet - Release 7.7.2 Acknowledge (bit 5.14) The ISO/IEC specification defines bit 5.14 as the Acknowledge bit. When this bit is a: • Zero, it indicates that the remote link partner has not received the ICS1893CF Link Control ...
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ICS1893CF Data Sheet Rev Release 7.8 Register 6: Auto-Negotiation Expansion Register Table 7-13 lists the bits for the Auto-Negotiation Expansion Register, which indicates the status of the Auto-Negotiation process. Note: For an explanation of acronyms used in Table ...
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ICS1893CF Data Sheet - Release 7.8.2 Parallel Detection Fault (bit 6.4) The ICS1893CF sets this bit to a logic one if a parallel detection fault is encountered. A parallel detection fault occurs when the ICS1893CF cannot disseminate the technology being ...
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ICS1893CF Data Sheet Rev Release 7.9 Register 7: Auto-Negotiation Next Page Transmit Register Table 7-14 lists the bits for the Auto-Negotiation Next Page Transmit Register, which establishes the contents of the Next Page Link Control Word that is ...
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... ICS1893CF Data Sheet - Release 7.9.1 Next Page (bit 7.15) This bit is used by a PHY/STA to enable the transmission of Next Pages following the base Link Control Word as long as the remote link partner supports the Next Page features of Auto-Negotiation. This bit is used to establish the state of the Next Page (NP) bit of the Next Page Link Control Word (that is, the NP bit of the Next Page Link Control Word tracks this bit) ...
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ICS1893CF Data Sheet Rev Release 7.10 Register 8: Auto-Negotiation Next Page Link Partner Ability Register Table 7-15 lists the bits for the Auto-Negotiation Next Page Link Partner Ability Register, which establishes the contents of the Next Page Link ...
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... ICS1893CF Data Sheet - Release 7.10.1 Next Page (bit 8.15) This bit is used by a PHY/STA to enable the transmission of Next Pages following the base Link Control Word as long as the remote link partner supports the Next Page features of Auto-Negotiation. This bit is used to establish the state of the Next Page (NP) bit of the Next Page Link Control Word (that is, the NP bit of the Next Page Link Control word tracks this bit) ...
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... ICS reserved 16.10 PHY Address Bit 4 16.9 PHY Address Bit 3 16.8 PHY Address Bit 2 16.7 PHY Address Bit 1 16.6 PHY Address Bit 0 16.5 Stream Cipher Test Mode Normal operation 16.4 ICS reserved 16.3 NRZ/NRZI encoding 16.2 Transmit invalid codes 16.1 ICS reserved 16 ...
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... PHY Address (bits 16.10:6) These five bits hold the Serial Management Port Address of the ICS1893CF. During either a hardware reset or a power-on reset, the PHY address is read from the LED interface. (For information on the LED interface, see Section 5.5, “Status Interface” ...
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ICS1893CF Data Sheet Rev Release 7.11.7 Invalid Error Code Test (bit 16.2) The Invalid Error Code Test bit allows an STA to force the ICS1893CF to transmit symbols that are typically classified as invalid. The purpose of this ...
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ICS1893CF Data Sheet - Release 7.12 Register 17: Quick Poll Detailed Status Register Table 7-18 lists the bits for the Quick-Poll Detailed Status Register. This register is a 16-bit read-only register used to provide an STA with detailed status of ...
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ICS1893CF Data Sheet Rev Release 7.12.1 Data Rate (bit 17.15) The Data Rate bit indicates the ‘selected technology’. If the ICS1893CF is in: • Hardware mode, the value of this bit is determined by the 10/100SEL input pin. ...
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ICS1893CF Data Sheet - Release Note: An MDIO read of these bits provides a history of the greatest progress achieved by the auto-negotiation process. In addition, the MDIO read latches the present state of the Auto-Negotiation State Machine for a ...
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ICS1893CF Data Sheet Rev Release 7.12.6 False Carrier (bit 17.8) The False Carrier bit indicates to an STA the detection of a False Carrier by the ICS1893CF in 100Base mode. A False Carrier occurs when the ICS1893CF begins ...
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ICS1893CF Data Sheet - Release 7.12.9 Premature End (bit 17.5) The Premature End bit indicates to an STA the detection of two consecutive Idles in a 100Base data stream by the ICS1893CF. During reception of a valid packet, the ICS1893CF ...
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ICS1893CF Data Sheet Rev Release 7.13 Register 18: 10Base-T Operations Register The 10Base-T Operations Register provides an STA with the ability to monitor and control the ICS1893CF activity while the ICS1893CF is operating in 10Base-T mode. Note: 1. ...
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ICS1893CF Data Sheet - Release 7.13.2 Polarity Reversed (bit 18.14) The Polarity Reversed bit is used to inform an STA whether the ICS1893CF has detected that the signals on the Twisted-Pair Receive Pins (TP_RXP and TP_RXN) are reversed. When the ...
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ICS1893CF Data Sheet Rev Release 7.13.8 Link Loss Inhibit (bit 18.1) The Link Loss Inhibit bit allows an STA to prevent the ICS1893CF from dropping the link in 10Base-T mode. When an STA sets this bit to logic: ...
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ICS1893CF Data Sheet - Release 7.14 Register 19: Extended Control Register 2 The Extended Control Register provides more refined control of the internal ICS1893CF operations. Note: 1. For an explanation of acronyms used in 2. During any write operation to ...
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... MDI or MDIX configuration to match the cable plant by automatically swapping transmit and receive signal pairs at the PHY. Auto-MDI/MDIX is defaulted on but may be disabled for test purposes using either the AMDIX_EN (pin 10 writing (bits 19. 9:8). See Table 7-22 for AMDIX_EN (19,9) and MDI_MODE (19,8) operation ...
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ICS1893CF Data Sheet - Release Table 7-22. AMDIX_EN (Pin 10) and Control Bits 19. 9:8 AMDIX_EN (Pin 10) 1 Default Values: 1 Definitions: straight transmit = TP_AP & TP_AN receive = TP_BP & TP_BN cross transmit = TP_BP & TP_BN ...
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ICS1893CF Data Sheet Rev Release Chapter 8 Pin Diagram, Listings, and Descriptions 8.1 ICS1893CF Pin Diagram POAC 1 VSS 2 P1CL 3 P2LI 4 VSS 5 P3TD 6 VDD 7 P4RD 8 10/100 9 AMDIX_EN 10 VSS 11 ...
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... RXD0 RXDV RXCLK RXER TXCLK TXEN TXD0 TXD1 TXD2 TXD3 COL CRS Table 8-2. ICS 1893CF Multifunction Pins: PHY Address and LED Pins Signal Name P4RD P3TD P2LI P1CL P0AC Table 8-3. ICS1893CF Configuration Pins Signal Name 10/100 AMDIX_EN 100TCSR 10TCSR ICS1893CF, Rev ...
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... Multi-Function (Multiplexed) Pins: PHY Address and LED Pins Table 8-5 lists the pins for the multi-function group of pins (that is, the multiplexed PHY Address / LED pins). Note: 1. During either a power-on reset or a hardware reset, each multi-function configuration pin is an input that is sampled when the ICS1893CF exits the reset state. After sampling is complete, these pins are output pins that can drive status LEDs ...
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... This multi-function configuration pin is: – An input pin during either a power-on reset or a hardware reset. In this case, this pin configures the ICS1893CF PHY Address Bit 1. – An output pin following reset. In this case, this pin provides collision status for the ICS1893CF input pin: • ...
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... This multi-function configuration pin is: – An input pin during either a power-on reset or a hardware reset. In this case, this pin configures the address of the ICS1893CF PHY Address Bit 2. – An output pin following reset. In this case, this pin provides link status for the ICS1893CF. ...
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... Input or Output ICS1893CF, Rev. J, 08/11/09 Chapter 8 Pin Diagram, Listings, and Descriptions Pin Description PHY (Address Bit Receive Data LED. For more information on this pin, see • This multi-function configuration pin is: – An input pin during either a power-on reset or a hardware reset. In this case, this pin configures the ICS1893CF when either hardware mode or software mode. – ...
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ICS1893CF Data Sheet Rev Release 8.2.3 Configuration Pins Table 8-6 lists the configuration pins. Table 8-6. Configuration Pins Pin Pin Name Number 10/100SEL 9 10TCSR 19 100TCSR 20 REF_IN 47 REF_OUT 46 RESETn 23 ICS1893CF, Rev. J, 08/11/09 ...
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ICS1893CF Data Sheet - Release 8.2.4 MAC Interface Pins This section lists pin descriptions for each of the following interfaces • Section 8.2.4.1, “MAC Interface Pins for Media Independent Interface” 8.2.4.1 MAC Interface Pins for Media Independent Interface Table 8-7 ...
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ICS1893CF Data Sheet Rev Release Table 8-7. MAC Interface Pins: Media Independent Interface (MII) (Continued) Pin Pin Pin Name Number Type MDIO 26 Input/ Output RXCLK 34 Output ICS1893CF, Rev. J, 08/11/09 Chapter 8 Pin Diagram, Listings, and ...
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ICS1893CF Data Sheet - Release Table 8-7. MAC Interface Pins: Media Independent Interface (MII) (Continued) Pin Pin Pin Name Number Type RXD0 31 Output RXD1 30 RXD2 29 RXD3 28 RXDV 32 Output RXER 35 Output TXCLK 37 Output ICS1893CF, ...
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ICS1893CF Data Sheet Rev Release Table 8-7. MAC Interface Pins: Media Independent Interface (MII) (Continued) Pin Pin Pin Name Number Type TXD0 39 Input TXD1 40 TXD2 41 TXD3 42 TXEN 38 Input ICS1893CF, Rev. J, 08/11/09 Chapter ...
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ICS1893CF Data Sheet - Release 8.2.5 Ground and Power Pins Table 8-8. Ground and Power Pins Signal Name VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS ICS1893CF, Rev. J, 08/11/09 Chapter 8 Pin ...
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ICS1893CF Data Sheet Rev Release 8.3 ICS1893CK Pin Diagram with MDIX Pinout (56L, 8x8 MLF2) 10/100 1 AMDIX_EN 2 VSS 3 TP_AP 4 TP_AN 5 VDD 6 VDD 7 TP_BN 8 TP_BP 9 VSS 10 VDD 11 10TCSR ...
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... RXD1 RXD0 RXDV RXCLK RXER TXCLK TXEN TXD0 TXD1 TXD2 TXD3 COL CRS Table 8-10. ICS1893CK Multifunction Pins: PHY Address and LED Pins Signal Name P4RD P3TD P2LI P1CL P0AC Table 8-11. ICS1893CK Configuration Pins Signal Name 10/100 AMDIX_EN 10TCSR 100TCSR ICS1893CF, Rev ...
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... Twisted Pair Transformers connections are shown in Chapter 5. The transformer must be 1:1 ratio and symetrical for 10/100 MDI/MDIX applications since the transmit twisted pair and receive twisted pair are interchangeable. ICS1893 PHYs do not have power connections to the Transformer. All transformer power is supplied by the ICS1893CK. ...
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ICS1893CF Data Sheet - Release 8.3.3 Ground and Power Pins Table 8-13. ICS1893CK Ground and Power Pins Signal Name VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS ...
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ICS1893CF Data Sheet Rev Release Chapter 9 DC and AC Operating Conditions 9.1 Absolute Maximum Ratings Table 9-1 lists absolute maximum ratings. Stresses above these ratings can permanently damage the ICS1893CF. These ratings, which are standard values for ...
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ICS1893CF Data Sheet - Release 9.3 Recommended Component Values * Table 9-3. Recommended Component Values for ICS1893CF Parameter Oscillator Frequency 10TCSR Resistor Value 100TCSR Resistor Value LED Resistor Value † There are two IEEE Std. 802.3 requirements that define the ...
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ICS1893CF Data Sheet Rev Release 9.4 DC Operating Characteristics This section lists the ICS1893CF DC operating characteristics. 9.4.1 DC Operating Characteristics for Supply Current Table 9-4 lists the DC operating characteristics for the supply current to the ICS1893CF ...
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ICS1893CF Data Sheet - Release 9.4.3 DC Operating Characteristics for REF_IN Table 9-6 lists the 3.3-V DC characteristics for the REF_IN pin. Note: The REF_IN input switch point is 50% of VDD. Table 9-6. 3.3-V DC Operating Characteristics for REF_IN ...
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ICS1893CF Data Sheet Rev Release 9.5 Timing Diagrams 9.5.1 Timing for Clock Reference In (REF_IN) Pin Table 9-8 lists the significant time periods for signals on the clock reference in (REF_IN) pin. shows the timing diagram for the ...
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ICS1893CF Data Sheet - Release 9.5.2 Timing for Transmit Clock (TXCLK) Pins Table 9-9 lists the significant time periods for signals on the Transmit Clock (TXCLK) pins for the various interfaces. Figure 9-3 shows the timing diagram for the time ...
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ICS1893CF Data Sheet Rev Release 9.5.3 Timing for Receive Clock (RXCLK) Pins Table 9-10 lists the significant time periods for signals on the Receive Clock (RXCLK) pins for the various interfaces. Figure 9-4 shows the timing diagram for ...
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ICS1893CF Data Sheet - Release 9.5.4 100M MII: Synchronous Transmit Timing Table 9-11 lists the significant time periods for the 100M MII Interface synchronous transmit timing. The time periods consist of timings of signals on the following pins: • TXCLK ...
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ICS1893CF Data Sheet Rev Release 9.5.5 10M MII: Synchronous Transmit Timing Table 9-12 lists the significant time periods for the 10M MII synchronous transmit timing. The time periods consist of timings of signals on the following pins: • ...
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ICS1893CF Data Sheet - Release 9.5.6 100M/MII Media Independent Interface: Synchronous Receive Timing Table 9-13 lists the significant time periods for the MII / 100M Stream Interface synchronous receive timing. The time periods consist of timings of signals on the ...
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ICS1893CF Data Sheet Rev Release 9.5.7 MII Management Interface Timing Table 9-14 lists the significant time periods for the MII Management Interface timing (which consists of timings of signals on the MDC and MDIO pins). Table 9-14. MII ...
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ICS1893CF Data Sheet - Release 9.5.8 10M Media Independent Interface: Receive Latency Table 9-15 lists the significant time periods for the 10M MII timing. The time periods consist of timings of signals on the following pins: • TP_RX (that is, ...
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ICS1893CF Data Sheet Rev Release 9.5.9 10M Media Independent Interface: Transmit Latency Table 9-16 lists the significant time periods for the 10M MII transmit latency. The time periods consist of timings of signals on the following pins: • ...
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ICS1893CF Data Sheet - Release 9.5.10 100M / MII Media Independent Interface: Transmit Latency Table 9-17 lists the significant time periods for the MII / 100 Stream Interface transmit latency. The time periods consist of timings of signals on the ...
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ICS1893CF Data Sheet Rev Release 9.5.11 100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) Table 9-18 lists the significant time periods for the 100M MII carrier assertion/de-assertion during half-duplex transmission. The time periods consist of timings of signals on the ...
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ICS1893CF Data Sheet - Release 9.5.12 10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) Table 9-19 lists the significant time periods for the 10M MII carrier assertion/de-assertion during half-duplex transmission. The time periods consist of timings of signals on the following pins: ...
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ICS1893CF Data Sheet Rev Release 9.5.13 100M MII Media Independent Interface: Receive Latency Table 9-20 lists the significant time periods for the 100M MII / 100M Stream Interface receive latency. The time periods consist of timings of signals ...
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ICS1893CF Data Sheet - Release 9.5.14 100M Media Independent Interface: Input-to-Carrier Assertion/De-Assertion Table 9-21 lists the significant time periods for the 100M MDI input-to-carrier assertion/de-assertion. The time periods consist of timings of signals on the following pins: • TP_RX (that ...
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ICS1893CF Data Sheet Rev Release 9.5.15 Reset: Power-On Reset Table 9-22 lists the significant time periods for the power-on reset. The time periods consist of timings of signals on the following pins: • VDD • TXCLK Figure 9-16 ...
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ICS1893CF Data Sheet - Release 9.5.16 Reset: Hardware Reset and Power-Down Table 9-23 lists the significant time periods for the hardware reset and power-down reset. The time periods consist of timings of signals on the following pins: • REF_IN • ...
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ICS1893CF Data Sheet Rev Release 9.5.17 10Base-T: Heartbeat Timing (SQE) Table 9-24 lists the significant time periods for the 10Base-T heartbeat (that is, the Signal Quality Error). The time periods consist of timings of signals on the following ...
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ICS1893CF Data Sheet - Release 9.5.18 10Base-T: Jabber Timing Table 9-25 lists the significant time periods for the 10Base-T jabber. The time periods consist of timings of signals on the following pins: • TXEN • TP_TX (that is, TP_TXP and ...
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ICS1893CF Data Sheet Rev Release 9.5.19 10Base-T: Normal Link Pulse Timing Table 9-26 lists the significant time periods for the 10Base-T Normal Link Pulse (which consists of timings of signals on the TP_TXP pins). Table 9-26. 10Base-T Normal ...
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ICS1893CF Data Sheet - Release 9.5.20 Auto-Negotiation Fast Link Pulse Timing Table 9-27 lists the significant time periods for the ICS1893CF Auto-Negotiation Fast Link Pulse. The time periods consist of timings of signals on the following pins: • TP_TXP • ...
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... ICS1893CF Data Sheet Rev Release Chapter 10 Physical Dimensions of ICS1893CF Package Figure 10-1. ICS1893CF 300 mil SSOP Physical Dimensions ICS1893CF, Rev. J, 08/11/09 Chapter 10 Physical Dimensions of ICS1893CF Copyright © 2009, Integrated Device Technology, Inc. All rights reserved. 123 August, 2009 ...
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... ICS1893CF Data Sheet - Release Figure 10-2. ICS1893CK Thermally Enhanced, Very Thin, Fine Pitch, Quad Flat / No Lead Plastic Package ICS1893CF, Rev. J, 08/11/09 Chapter 10 Physical Dimensions of ICS1893CF Copyright © 2009, Integrated Device Technology, Inc. All rights reserved. 124 August, 2009 ...
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ICS1893CF Data Sheet Rev Release Chapter 11 Ordering Information Figure 11-1. shows ordering information for the ICS1893CF. *NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01. Part / Order Number ICS1893CF* ICS1893CFLF ICS1893CFT* ICS1893CFLFT ICS1893CFI* ...
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ICS1893CF Data Sheet - Release 11.1 Marking Diagram Notes: 1. Line 3: ###### = Lot number. 2. Line 4: YYWW = Date code. 3. Line 5: Origin. ICS1893CF, Rev. J, 08/11/09 Copyright © 2009, Integrated Device Technology, Inc. All rights ...
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ICS1893CF Data Sheet Rev Release Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. www.idt.com ICS1893CF, Rev. J, 08/11/09 For Tech Support www.idt.com/go/clockhelp Copyright © ...