ICS1892Y-14LF IDT, Integrated Device Technology Inc, ICS1892Y-14LF Datasheet - Page 50

• Manufacturer Part Number: ICS1892Y-14LF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of ICS1892Y-14LF

• Lead Free Status / RoHS Status: Compliant

7.5.4 10Base-T Operation: Idle
7.5.5 10Base-T Operation: Link Monitor
ICS1892, Rev. D, 2/26/01
The ICS1892 10Base-T Idle Function transmits link pulses in the absence of data (that is, when the
MAC/repeater is not requiring it to transmit any data). During this time the link is Idle, and the 10Base-T Idle
Function begins periodically transmitting link pulses at a rate of one pulse every 16 ms, as defined in the
ISO/IEC 8802-3 standard. In 10Base-T mode, the ICS1892 transmits link pulses whenever the
MAC/repeater does not have any data available for transmission. The ICS1892 continues transmitting link
pulses while receiving data. Because link pulses indicate an idle state for a link, this situation does not
generate a Collision Detect signal (COL).
When the ICS1892 is in 10Base-T mode, the Link Monitor Function observes the data received by the
10Base-T Twisted-Pair Receiver to determine the link status. The results of this continual monitoring are
stored in the Link Status bit. The Station Management entity (STA) can access the Link Status bit in either
the Status Register (bit 1.2) or the QuickPoll Detailed Status Register (bit 17.0). This Link Status bit is a
latching low (LL) bit. (For more information on latching high and latching low bits, see
“Latching High Bits”
The STA can control the execution of the Smart Squelch Function using bit 18.0 (the Smart Squelch Inhibit
bit in the 10Base-T Operations Register). The Squelch Inhibit bit allows an STA to control the ICS1892
Squelch Detection in 10Base-T mode. When an STA sets this bit to logic:
•
•
The criteria used by the Link Monitoring Function to declare a link either valid (that is, ‘established’ or ‘up’)
or invalid (that is, ‘failed’ or ‘down’) depends upon the present state of the link and the incoming data. When
the 10Base-T link is:
•
•
Note:
1. When the link is invalid and the ICS1892 detects the presence of data, the ICS1892 does not transition
2. Enabling or disabling the Smart Squelch Function affects the Link Monitor function.
3. A transition from the invalid state to the valid state does not automatically update the LL Link Status bit.
Zero, before the ICS1892 can establish a valid link, the ICS1892 must receive valid 10Base-T data.
One, before the ICS1892 can establish a valid link, the ICS1892 must receive both valid 10Base-T data
followed by an IDL.
Valid, the Link Monitor Function continues to report the link as valid as long as it detects either data or
Normal Link Pulses (NLPs) on its Twisted-Pair Receiver. If the 10Base-T Operations Register’s Smart
Squelch Inhibit bit (bit 18.0) is:
Invalid, the Link Monitor Function must detect one of three events before transitioning the link from the
invalid state to the valid state. If the ICS1892 receives any of the following it changes the status of the
link from invalid to valid:
The ICS1892 receives data when the Twisted-Pair Receiver phase-locked loop can acquire lock and
extract the receive clock from the incoming data stream for three bit times.
If the ICS1892 receives neither data nor NLPs (that is, the link shows either no activity or inconsistent
activity) for more than 81 to 83 ms, then the ICS1892 declares the link invalid and sets the LL Link Status
bit to logic zero. The LL Link Status bit remains latched in the cleared state until a reset occurs or until
the STA reads it while the link is valid.
– Enabled, before the 10Base-T link can be valid, there must be an IDL at the end of a data packet.
– Disabled, before the 10Base-T link can be valid, all that is needed is a data packet.
– More than seven Normal Link Pulses (NLPs)
– Any data
– Any data followed by a valid IDL
the link to the valid state until after the reception of the present packet is complete.
ICS1892 Data Sheet
and
Section 8.1.4.2, “Latching Low
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
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Bits”.)
Chapter 7 Functional Blocks
Section 8.1.4.1,
February 26, 2001