HBLXT9785HE Cortina Systems Inc, HBLXT9785HE Datasheet - Page 184

• Manufacturer Part Number: HBLXT9785HE
• Manufacturer: Cortina Systems Inc

Specifications of HBLXT9785HE

• Lead Free Status / RoHS Status: Not Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Table 73
Figure 52
Table 74
Cortina Systems
RMII - 100BASE-TX Receive Timing Parameters
RMII - 100BASE-TX Transmit Timing
RMII - 100BASE-TX Transmit Timing Parameters
®
RxData<1:0>, CRS_DV, RXER setup to REFCLK
rising edge
RxData<1:0>, CRS_DV, RXER hold from REFCLK
rising edge
Receive start of /J/ to CRS_DV asserted
Receive start of /T/ to CRS_DV de-asserted
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
3. Values and conditions from RMII Specification, Rev. 1.2.
Note:
TxData<1:0>/TxEN setup to REFCLK rising
edge
TxData<1:0>/TxEN hold from REFCLK rising
edge
TxEN sampled to TPFO out (Tx latency)
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
Note:
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
testing.
100BASE-TX or 100BASE-FX).
testing.
100BASE-TX or 100BASE-FX).
The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
TxData(1:0)
3
3
REFCLK
TPFO
TxEN
Parameter
Parameter
t
1
t
3
Sym
t1
t2
t3
Sym
t1
t2
t3
t4
t
1
Min
4
2
–
t
Min
2
4
2
–
–
Typ1
12
Typ1
–
–
16
20
–
–
Max
17
Max
–
–
14
14
21
27
6.0 Test Specifications
Units
BT
Units
ns
ns
BT
BT
ns
ns
2
2
2
t
2
Conditions
Conditions
Test
Test
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