HBLXT9785HE Cortina Systems Inc, HBLXT9785HE Datasheet - Page 36

• Manufacturer Part Number: HBLXT9785HE
• Manufacturer: Cortina Systems Inc

Specifications of HBLXT9785HE

• Lead Free Status / RoHS Status: Not Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
3.2
3.2.1
3.2.2
Table 5
Cortina Systems
PQFP Signal Descriptions
Signal Name Conventions
Signal names may contain either a port designation or a serial designation, or a
combination of the two designations. Signal naming conventions are as follows:
PQFP Signal Descriptions – RMII, SMII, and SS-SMII
Configurations
Table 5
signal descriptions. Ball designations are included for cross-reference.
RMII Signal Descriptions – PQFP (Sheet 1 of 3)
®
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID
3. RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are three-stated in Isolation and H/W
• Port Number Only. Individual signals that apply to a particular port are designated by
• Serial Number Only. A set of signals which are not tied to any specific port are
• Port and Serial Number. In cases where each port is assigned a set of multiple
PQFP
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Designation
44
61
62
52
53
42
43
6
the Signal Mnemonic, immediately followed by the Port Designation. For example,
Transmit Enable signals would be identified as TxEN0, TxEN1, and TxEN2.
designated by the Signal Mnemonic, followed by an underscore and a serial
designation. For example, a set of three Global Configuration signals would be
identified as CFG_1, CFG_2, and CFG_3.
signals, each signal is designated in the following order: Signal Mnemonic, Port
Designation, an underscore, and the serial designation. For example, a set of three
Port Configuration signals would be identified as RxData0_0 and RxData0_1,
RxData1_0 and RxData1_1, and RxData2_0 and RxData2_1.
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-
Down.
resistors are also disabled when the output is enabled.
Power-Down modes and during H/W reset.
Pin-Ball
through
PBGA
E12
E6,
E2,
C3,
D4
B5
A4
F4
Table 17, Receive FIFO Depth Considerations, on page 50
TxData0_0
TxData0_1
TxData1_0
TxData1_1
TxData2_0
TxData2_1
REFCLK0
REFCLK1
Symbol
Type
I, ID
I, ID
I, ID
I
1
Signal Description
Reference Clock.
50 MHz RMII reference clock is always required. RMII
inputs are sampled on the rising edge of REFCLK,
RMII outputs are sourced on the falling edge.
Transmit Data - Port 0.
Inputs containing 2-bit parallel di-bits to be transmitted
from port 0 are clocked in synchronously to REFCLK.
Transmit Data - Port 1.
Inputs containing 2-bit parallel di-bits to be transmitted
from port 1 are clocked in synchronously to REFCLK
Transmit Data - Port 2.
Inputs containing 2-bit parallel di-bits to be transmitted
from port 2 are clocked in synchronously to REFCLK.
2,3
3.2 PQFP Signal Descriptions
provide PQFP
Page 36