HBLXT9785HE Cortina Systems Inc, HBLXT9785HE Datasheet - Page 195

• Manufacturer Part Number: HBLXT9785HE
• Manufacturer: Cortina Systems Inc

Specifications of HBLXT9785HE

• Lead Free Status / RoHS Status: Not Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Figure 63
Table 88
Cortina Systems
PHY Identifier Bit Mapping
Auto-Negotiation Advertisement Register (Address 4)
®
1. R/W = Read/Write, R = Read Only
2. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as
3. The default setting of Register bit 4.10 is determined by the PAUSE pin. The BGA15 package does not
4. Default settings for bits 4.5:8 are determined by CFG pins as described in
5. Pause operation is only valid for full-duplex modes.
6. If Register bit 4.13 is set to advertise a fault, Register bit 1.4 will be set. Register bit 4.13 is set or cleared
Note:
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
13
Bit
15
14
12
11
10
the pin(s) are latched at startup or hardware reset.
have a Pause hardware configuration pin and has a default of 0.
Configuration Settings , on page
only through the MDC/MDIO interface and is not cleared upon completion of auto-negotiation.
6
Restart the auto-negotiation process whenever Register 4 is written/modified.
Name
Remote Fault
Asymmetric
Next Page
Reserved
Reserved
I/G
a
1
0
Pause
Pause
b
2
0
0
1
3
0
c
5
5
0
00
0
0
Organizationally Unique Identifier
PHY ID Register #1 (Address 2)
0
Description
0 = Port has no ability to send manual next pages
1 = Port has ability to send manual next pages
Note: This bit should only be set to manually control the auto-
negotiation process. It is not needed and should be cleared
for DTE Discovery.
Write as 0, ignore on Read
0 = No remote fault
1 = Remote fault
Write as 0, ignore on Read
Pause operation defined in Clause 40 and 27
0 = Port is not Pause capable
1 = Port can only send Pause
0 = Pause operation disabled
1 = Port can send and receive Pause
Note:
0
0
0
The Cortina OUI is 00207B hex.
0
0
Default for the BGA15 package is 0.
0
0
126.
0
0
20
1
0
1
2
0
0
3
1
18 19
r
0
1
B
1
s
0
5
1
7B
1
PHY ID Register #2 (Address 3)
1
7
1
24
10
0
x
9
X
5
Manufacturer's
Model Number
X
X
Table 42, Global Hardware
X
X
7.0 Register Definitions
X
4
0
X
3
3
Revision
Number
Type
X
R/W
R/W
R/W
R/W
R/W
Variant
R
Model
X
1
1
0
X
0
Page 195
LSHR
Default
0
0
0
0
0
2,3