CY7C9689A-AC Cypress Semiconductor Corp, CY7C9689A-AC Datasheet - Page 16

• Manufacturer Part Number: CY7C9689A-AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C9689A-AC

• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02020 Rev. *D
The CY7C9689A contains an integrated 4B/5B encoder that
accepts 8-bit data characters and converts these into 10-bit
transmission characters that have been optimized for
transport on serial communications links. This 4B/5B encoding
scheme is compliant with the ANSI X3T9.5 (FDDI)
committee’s 4B/5B code. The CY7C9689A also contains a
5B/6B encoder that accepts 10-bit data characters and
converts these into 12-bit transmission characters.
The 4B/5B, 5B/6B encoder can be bypassed for those
systems that operate with external 4B/5B or 5B/6B encoders
or use alternate forms of encoding or scrambling to ensure
good transmission characteristics. The complete encoding
tables are listed in
When the Encoder is enabled, the transmit data characters (as
passed through the Transmit FIFO and pipeline register) are
converted to either a 10-bit or 12-bit Data symbol or a 10-bit or 12-bit
Command Character, depending upon the state of the TXSC/D
input. If TXSC/D is HIGH, the data on the command inputs are
encoded into Command Character as shown in
is LOW, the data inputs are encoded using the Data Character
encoding in
The 4B/5B, 5B/6B coding function of the Encoder can be
bypassed for systems that include an external coder or
scrambler function as part of the controller or host system. This
is performed by setting ENCBYP LOW. With the encoder
bypassed, each 10-bit or 12-bit character (as captured in the
Transmit Input Register) is passed directly to the Transmit
Shifter (or Transmit FIFO) without modification.
Transmit Shifter
The Transmit Shifter accepts 10-bit (BYTE8/10 = HIGH) or
12-bit (BYTE8/10 = LOW) parallel data from the Encoder block
once each character time, and shifts it out the serial interface
output buffers using a PLL-multiplied bit-clock with NRZI
encoding. This bit-clock runs at 2.5, 5, or 10 times the REFCLK
rate (3, 6, or 12 times when BYTE8/10 is LOW) as selected by
RANGESEL and SPDSEL (see
parallel transfer is controlled by the counter and dividers in the
Clock Multiplier PLL and is not affected by signal levels or
timing at the input pins. Bits in each character are shifted out
LSB first.
Table
7.
Table 7
and
Table
Table
8.
3). Timing for the
Table
8. If TXSC/D
Routing Matrix
The Routing Matrix is a precision multiplexor that allows local
diagnostic loopback. The signal routing for the transmit serial
outputs is controlled by the DLB input as listed
Table 2. Transmit Data Routing Matrix
Serial Line Drivers
The serial interface PECL Output Drivers (ECL referenced to
+5V) are the transmission line drivers for the serial media.
OUTA± receives its data directly from the transmit shifter, while
OUTB± receives its data from the Routing Matrix. These two
outputs (OUTA± and OUTB±) are capable of direct connection
to +5V optical modules, and can also directly drive DC- or
AC-coupled transmission lines.
The PECL-compatible Output Drivers can be viewed as
programmable current sources. The output voltage is deter-
mined by the output current and the load impedance Z
The desired output voltage swing is therefore controlled by the
current-set resistor R
Different R
impedance/amplitude combinations. The output swing is
designed to center around V
externally biased to V
This differential output-swing can be specified two ways: either
as a peak-to-peak voltage into a single-end load, or as an
absolute differential voltage into a differential load.
When specified into a single-ended load (one of the outputs
switching into a load), the single output will both source and
sink current as it changes between its HIGH and LOW levels.
The voltage difference between this HIGH level and LOW level
determine the peak-to-peak signal-swing of the output. This
amplitude relationship is controlled by the load impedance on
the driver, and by the resistance of the R
that driver, as listed in
In
of the differential driver when that output is driving HIGH and
R
DLB[0]
Eq.
CURSET
0
1
1, V
OPP
CURSET
=
is the difference in voltage levels at one output
180
--------------------------------- -
A/B
A/B
INB
INA
INB
INA
V
×
values are required for different line
DD
OPP
Eq. 1
Z
CURSET
–1.33V.
TRANSMIT
TRANSMIT
LOAD
SHIFTER
SHIFTER
Data Connections
DD
associated with that driver.
–1.33V. Each output must be
RECEIVE
RECEIVE
PLL
PLL
CY7C9689A
CURSET
Page 16 of 51
Table
resistor for
OUTA
OUTB
OUTA
OUTB
2.in
LOAD
Eq. 1
.
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