CY7C9689A-AC Cypress Semiconductor Corp, CY7C9689A-AC Datasheet - Page 39

• Manufacturer Part Number: CY7C9689A-AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C9689A-AC

• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02020 Rev. *D
the device is not addressed (CE is not sampled LOW), the flag
remains set internally regardless of the number of TXCLK
clock cycles that are processed. If the device status is not
polled on a sufficiently regular basis, it is possible for the host
system to miss one or more of these BIST loop indications.
A pass through the loop is defined as that condition where the
Encoder generates the 0x00 (where 0x denotes Hex number,
e.g. 0x00 denotes HEX00) state. Depending on the initial state
of the BIST LFSR, the first pass through the loop may occur at
substantially less than 511 character periods. Following the
first pass, as long as TXBISTEN remains LOW, all remaining
passes are exactly 511 characters in length.
When the Transmit FIFO is bypassed, the interface is clocked
by the REFCLK signal instead of TXCLK. While the active or
asserted state of the TXEMPTY signal is still controlled by the
EXTFIFO, the state of any completed BIST loops is no longer
preserved. Instead, the TXEMPTY flag reflects the dynamic
state of the BIST loop progress, and is asserted only once
every 511 character periods. If the interface is not addressed
at the time that this occurs, then the FIFO status flags remain
in a high-Z state and the loop event is lost.
BIST Receive Path
The receive path operation in BIST is similar to that of the
transmit path. While the Receive FIFO is enabled (not
bypassed) and RXBISTEN is recognized internally, all writes
to the Receive FIFO are suspended.
Any data present in the Receive FIFO when RXBISTEN is
recognized remains in the FIFO and cannot be read until the
BIST operation is complete. The data in the Receive FIFO
remains valid, but is NOT available for reading through the
host parallel interface. This is because the error output
indicator for receive BIST operations is the VLTN signal, which
is normally part of the RXDATA bus. To prevent read opera-
tions while BIST is in operation, the RXEMPTY and RXHALF
flags are forced to indicate an Empty condition. Once
RXBISTEN has been removed and recognized internally, the
Receive FIFO status flags are updated to reflect the current
content status of the Receive FIFO.
To allow removal of stale data from the Receive FIFO, it may
be reset during a BIST operation. The reset operation
proceeds as documented, with the exception that the
RXEMPTY and RXHALF status flags already indicate an
empty condition. The RXFULL flag is used to present BIST
progress. The active (asserted) state on RXFULL (and
RXEMPTY) remain controlled by the present operating mode
and interface timing model (UTOPIA or Cascade).
When RXBISTEN has been recognized, RXFULL becomes
the receive BIST loop indicator (regardless of the logic state of
FIFOBYP). When RXBISTEN is first recognized, the RXFULL
flag is clocked to a set state, regardless of the addressed state
of the Receive FIFO (if CE is sampled LOW or not). Following
this, RXFULL remains set until the receiver detects the start of
the BIST pattern. Then RXFULL is deasserted for the duration
of the BIST pattern, pulsing asserted for one RXCLK period on
the last symbol of each BIST loop. If 14 of 28 consecutive
characters are received in error, RXFULL returns to the set
state until the start of a BIST sequence is again detected.
Just like the BIST status flag on the transmit data path, the
RXFULL flag captures the asserted states, and keeps them
until they are read. This means that if the status flag is not read
on a regular basis, events may be lost.
The detection of errors is presented on the VLTN output.
Unlike the RXFULL FIFO status flag, the active state of this
output is not controlled by the EXTFIFO input. With the
Receive FIFO enabled, these outputs should operate the
same as the RXFULL flag, with respect to preserving the
detection state of an error until it is read.
Unlike the RXFULL flag, which only needs the CY7C9689A to
be addressed (CE sampled LOW by RXCLK) to enable the
RXFULL three-state driver, and an RXCLK to “read” the flag,
the VLTN output requires a selection (assertion of RXEN while
addressed) to enable the RXDATA bus three-state drivers.
The selection process is necessary to ensure that a multi-PHY
implementation does not enable multiple VLTN drivers at the
same time.
When the Receive FIFO is bypassed, the interface is clocked
by the RXCLK output signal. While the active or asserted state
of the RXFULL signal is still controlled by the EXTFIFO input,
the state of any completed BIST loops or detected errors are
no longer preserved. Instead, the RXFULL flag reflects the
dynamic state of the BIST loop progress, and is asserted only
once every 511 character periods. If the interface is not
addressed at the time that this occurs, then the FIFO status
flags remain in a high-Z state and the loop event is lost. This
is also true of the VLTN output, such that if the CY7C9689A
receive path is not selected to enable the RXDATA bus
three-state drivers, the detection of a BIST miscompare is lost.
BIST Three-state Control
When BIST is enabled on either the transmitter or the receiver,
the three-state enable signals for the BIST status flags and
error indicators work the same as for normal data processing.
The output drivers for the BIST status that is presented on
FIFO status flags are only enabled when CE has been
sampled asserted (LOW) by the respective clock (TXCLK,
RXCLK, or REFCLK).
To access the BIST error information, it is necessary to
perform a read cycle of the addressed receiver. This means
that CE must be LOW to enable the receiver (Rx_Match), and
RXEN must be asserted from HIGH to LOW to select the
device. Because the part is in BIST, no data is read from the
FIFO, but the data bus is driven. This allows the VLTN indicator
to be driven onto the RXDATA bus. So long as RXEN remains
asserted, the receiver stays selected, the data bus remains
driven, and VLTN has meaning.
Bus Interfacing
The parallel transmit and receive host interfaces to the
CY7C9689A are configurable for either synchronous or
asynchronous operation. Each of these configurations
supports two selectable timing and control models of Shared
Bus or Cascade.
All asynchronous bus configurations have the internal
Transmit and Receive FIFOs enabled. This allows data to be
written or read from these FIFOs at any rate up to the
maximum 50-MHz clock rate of the FIFOs. All internal opera-
tions of the CY7C9689A do not use the external TXCLK or
RXCLK, but instead make use of synthesized derivatives of
CY7C9689A
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