CY7C9689A-AC Cypress Semiconductor Corp, CY7C9689A-AC Datasheet - Page 40

• Manufacturer Part Number: CY7C9689A-AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C9689A-AC

• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02020 Rev. *D
REFCLK for transmit path operations and a recovered
character clock for receive path operations.
All synchronous bus configurations require the bus interface
operations to be synchronous to REFCLK on the transmit path
and the recovered clock (output as RXCLK) on the receive
path. The internal FIFOs are bypassed in all synchronous
modes.
The two supported timing and control models are Shared Bus
and Cascade. The Shared Bus is based on the timing model
of a FIFO with active LOW FIFO status flags and read/write
enables.
The Cascade timing model is a modification of the Shared Bus
model that changes the flags and FIFO read/write enables to
active HIGH. This model is present primarily to allow depth
expansion of the internal FIFO by direct coupling to external
CY7C42x5 synchronous FIFOs. To allow this direct coupling,
the cycle-to-cycle timing between the transmit and receive
enables (TXEN and RXEN) are also modified to ensure correct
data transfer.
These four configurations of bus operation and timing/control
can all be used with or without external FIFOs. Depending on
the specific mode selected, the amount of external hardware
necessary to properly couple the CY7C9689A to state
machines or external FIFOs is minimal in all cases, and may
be zero if the proper configuration is selected.
With only minor exceptions, all configurations of the
CY7C9689A in the Shared Bus mode borrowed concepts from
the ATM Forum’s UTOPIA Bus operation. concepts of
addressing and selection to control the enabled/disabled state
of the output drivers, and when data can be written to or read
from the part.
Shared Bus Interface Concept
The CY7C9689A Parallel Interface is designed for interfacing
to a Shared Bus. The maximum TXCLK and RXCLK frequency
is 50 MHz, which provides a total bandwidth of 50Million
characters per second in each direction. More than two
CY7C9689A can be serviced on the same bus at full serial line
speed.
The CY7C9689A is designed to be the Slave in Master-Slave
type of shared bus architecture. Generally, the bus Master (a
Medium Access Device, MAC) is a higher layer device that
sources out going data/command and sinks incoming
data/command to/from Slaves (CY7C9689A) on the shared
bus (see
CY7C9689A
CE1
Figure
Figure 6. Shared Bus Architecture
CY7C9689A
6)
CE2
Master
Bus
............
Status, Control
TXDATA/TXCMD
RXDATA/RXCMD
CEn
CY7C9689A
The data bus (TXDATA, RXDATA), command bus (TXCMD,
RXCMD) and FIFO status flags (TXFULL, RXEMPTY, etc.) of
each CY7C9689A on the shared bus can be connected
together respectively. Each Slave can be assigned an
address. The address of each Slave can be decoded by a
decoder which drives the CE input of each Slave. The bus
Master will poll each Slave by selecting (or “Addressing”) the
device, and sample the FIFO flags. Depending on the FIFOs
status on each Slave device, the Master can schedule read
accesses to Slaves which have data in the RXFIFOs, and write
accesses to Slaves which have room in the TXFIFOs. While
data is being transferred on the data/command bus, the bus
Master can continue to poll each Slave device independently.
Device Selection
All actions on the Shared Bus interface are controlled by the
Chip Enable and selection states of the interface. These states
control the read and write access to the Receive and Transmit
FIFOs, access to the FIFO status flags, reset of the Transmit
and Receive FIFOs, and read and write access to the Serial
Address Register. The CY7C9689A supports the concept of
an “address match” through a single Chip Enable (CE) input.
Address Match and FIFO Flag Access
The CY7C9689A makes use of a single active-LOW Chip
Enable (CE) to generate address-match conditions. This
allows multiple CY7C9689A devices to share a common bus,
with device output three-state controls being managed by
either an address match condition (CE sampled LOW), or by
a selection state.
The Transmit and Receive FIFO flag output drivers are
enabled in any TXCLK, REFCLK, or RXCLK cycle following
CE being sampled asserted (LOW) by the rising edge of the
respective clock. The CE input is sampled separately by the
clocks for the transmit and receive interfaces, which allows
these clocks to be both asynchronous to each other, and to
operate at different clock rates. An example of both Transmit
and Receive FIFO flag access is shown in
RXEMPTY
TXFULL
RXCLK
TXCLK
CE
CE
Figure 7. FIFO Flag Driver Enables.
Transmit Port Addressing
Receive Port Addressing
Valid
Valid
CY7C9689A
Figure 7
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