ICS1892Y-10 IDT, Integrated Device Technology Inc, ICS1892Y-10 Datasheet - Page 97
ICS1892Y-10
Manufacturer Part Number
ICS1892Y-10
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.ICS1892Y-10.pdf
(148 pages)
Specifications of ICS1892Y-10
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8.13.8 Link Loss Inhibit (bit 18.1)
8.13.9 Squelch Inhibit (bit 18.0)
ICS1892, Rev. D, 2/26/01
The Link Loss Inhibit bit allows an STA to prevent the ICS1892 from dropping the link in 10Base-T mode.
When an STA sets this bit to logic:
•
•
The Squelch Inhibit bit allows an STA to control the ICS1892 Squelch Detection in 10Base-T mode. When
an STA sets this bit to logic:
•
•
Zero, the state machine behaves normally and the link status is based on the signaling detected Twisted-
Pair Receiver inputs.
One, the ICS1892 10Base-T Link Integrity Test state machine is forced into the ‘Link Passed’ state
regardless of the Twisted-Pair Receiver input conditions.
Zero, before the ICS1892 can establish a valid link, the ICS1892 must receive valid 10Base-T data.
One, before the ICS1892 can establish a valid link, the ICS1892 must receive both valid 10Base-T data
followed by an IDL.
ICS1892
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
97
Chapter 8 Management Register Set
February 26, 2001
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