MC33989PEG Freescale Semiconductor, MC33989PEG Datasheet - Page 23

• Manufacturer Part Number: MC33989PEG
• Description: SBC-HS
• Manufacturer: Freescale Semiconductor

TIM register description. Watchdog can only be cleared within the open window time. An attempt to clear the watchdog in the
closed window will generate a reset. Watchdog is cleared through SPI by addressing the TIM1 register.
RESET PIN DESCRIPTION
refer to
• V
• Power-on reset — At device power-on or at device wake-up from Sleep mode, the reset is maintained low until V
RST
Table 5. Reset and Watchdog Output Operation
RESET AND WATCHDOG OPERATION: MODES1 AND 2
through the SPI (register MCR, bit SAFE). Default mode after reset is Mode 1.
of operation. Two modes (modes 1 and 2) are available and can be selected through the SPI Safe bit. Default operation, after
reset or power-up, is Mode 1.
• In mode 1–Reset is activated in case of V
• In mode 2–(Safe mode) Reset is not activated in case of watchdog fault. WD output has the same behavior as in mode 1–The
Analog Integrated Circuit Device Data
Freescale Semiconductor
Notes
Devices Power-up
V
V
Watchdog Timeout Reached
V
V
Watchdog Timeout Reached
27.
1. Mode 1
2. Mode 2 (also called Safe mode)
A reset output is necessary and available to reset the microcontroller. Modes 1 and 2 are available for the reset pin (please
Reset causes when SBC is in mode 1:
returns to the normal voltage.
its operation range.
Watchdog timeout — If watchdog is not cleared, the SBC will pull the reset pin low for the duration of the reset time (parameter
In Mode 2, the reset pin is not activated in case of Watchdog timeout. Please refer to
For debug purposes at 25 °C, the Reset pin can be shorted to 5.0 V because of its internal limited current drive capability.
Watchdog and Reset functions have two modes of operation:
These modes are independent of the SBC modes (Normal, Standby, Sleep, and Stop). Modes 1 and 2 selection is achieved
Table 5
In both modes reset is active at device power-up and wake-up.
low. It remains low as long as the watchdog is not properly re-activated by the SPI.
Watchdog output pin is a push-pull structure driving external components of the application for signal instance of an MCU
wrong operation.
DD1
DD1
DD1
DD1
DD1
DUR)
Normal Watchdog Properly Triggered
Normal Watchdog Properly Triggered
< RST
< RST
WD stays low until the Watchdog register is properly addressed through SPI.
Table 5
falling out of range — If V
.
provides Reset and Watchdog output mode
TH
TH
for reset pin operation).
Events
DD1
falls below the reset threshold (parameter R
DD1
fall or watchdog not triggered. WD output is active low as soon as reset goes
1 or 2 (Safe Mode)
2 (Safe Mode)
2 (Safe Mode)
2 (Safe Mode)
Mode
1
1
1
RESET AND WATCHDOG PINS, SOFTWARE WATCHDOG OPERATIONS
STTH
), the RST pin is pulled low until V
WD Output
Low to High
Table 6
Low (Note)
Low (Note)
High
High
High
High
FUNCTIONAL DEVICE OPERATION
for more detail.
Reset Output
Low to High
DD1
High
High
High
Low
Low
Low
is within
DD1
33989
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