MC33989PEG Freescale Semiconductor, MC33989PEG Datasheet - Page 48

• Manufacturer Part Number: MC33989PEG
• Description: SBC-HS
• Manufacturer: Freescale Semiconductor

TYPICAL APPLICATIONS
SUPPLEMENTAL APPLICATION NOTES
MC33989 CAN INTERFACE
Block Diagram
CAN Interface Supply
the pin VSUP. This path is used in CAN sleep mode to allow wake-up detection.
low power mode, the current is sourced from the VSUP pin.
Main Operation Modes Description
by the SPI command.
CAN Driver Operation in Normal Mode
is controlled by the TX pin. The bus state is reported through the RX pin.
2, approx. 2.5 V.
pulled high toward 5.0 V (the voltage at V2).
mV). If “CANH minus CANL” is below the threshold, the bus is recessive and RX is set high.
48
33989
• T1: Is dependent on the selected cyclic sense timing in the TIM2 register (5.0 to 400 ms). LX is sampled 10 µs before the
• T2: It is the same than Lx to INT pulse: typ 100 µs
• The total time is around 5.13 ms (for a cyclic sense total time of 5.0 ms) in the above example.
This section is a detailed description of the CAN interface of the MC33989.
Figure 34
The supply voltage for the CAN driver is the V2 pin. The CAN interface also has a supply path from the battery line, through
During CAN communication (transmission and reception) the CAN interface current is sourced from the V2 pin. During a CAN
The CAN interface of the MC33989 has two main operation modes: Normal mode and sleep mode. The modes are controlled
In normal mode, used for communication, four different slew rates are available for the user.
In sleep mode, the user has the option to enable or disable the remote CAN wake-up capability.
When the CAN interface of the MC33989 is in Normal mode, the driver has two states: recessive or dominant. The driver state
When TX is high, the driver is set in a recessive state, CANH and CANL lines are biased to the voltage set at V2 divided by
When TX is low, the bus is set into dominant state: the CANL and CANH drivers are active. CANL is pulled to gnd, CANH is
The RX pin reports the bus state: the CANH minus the CANL voltage is compared versus an internal threshold (a few hundred
end of cyclic sense on time. If the LX correct wake-up level happens just after sample point, the wake-up will be detected
at the next HS1 activation and a complete period is lost.
is a simplified block diagram of the CAN interface of the MC33989.
VSUP
RX
TX
wake-up
Internal
signal
V2
SPI control
SPI control
Differential
V2
receiver
Wake-up
pattern
recognition
Figure 34. 33989 CAN Interface
SPI control
Driver
Driver
2.5V
V2
V2
Wake- up
receiver
V2
QL
QH
CANH
CANL
Bus termination (60 ohms)
CANH line
CAN L line
Analog Integrated Circuit Device Data
Freescale Semiconductor