PIC16F721-E/SO Microchip Technology, PIC16F721-E/SO Datasheet
PIC16F721-E/SO
Specifications of PIC16F721-E/SO
Related parts for PIC16F721-E/SO
PIC16F721-E/SO Summary of contents
Page 1
... Microchip Technology Inc. PIC16F/LF720/721 20-Pin Flash Microcontrollers with nanoWatt XLP Technology Data Sheet DS41430A ...
Page 2
... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
Page 3
... Flash Microcontrollers with nanoWatt XLP Technology Devices Included In This Data Sheet: • PIC16F720 • PIC16LF720 • PIC16F721 • PIC16LF721 High-Performance RISC CPU: • Only 35 Instructions to Learn: - All single-cycle instructions except branches • Operating Speed – 16 MHz oscillator/clock input - DC – 250 ns instruction cycle • ...
Page 4
... PIC16F/LF720/721 Program Memory SRAM Device Flash (bytes) (words) PIC16F720 2048 128 PIC16F721 4096 256 PIC16LF720 2048 128 PIC16LF721 4096 256 DS41430A-page 4 Timers 8-bit A/D I/O AUSART 8/16-bit (ch) 18 2/1 12 Yes 18 2/1 12 Yes 18 2/1 12 Yes 18 2/1 12 Yes CCP SSP 2010 Microchip Technology Inc. ...
Page 5
... Pin Diagrams – 20-PIN DIAGRAM FOR PIC16F720/721 AND PIC16LF720/721 PDIP, SOIC, SSOP RA5/T1CKI/CLKIN RA4/AN3/T1G/CLKOUT RA3/MCLR/V RC6/AN8/SS RC7/AN9/SDO Pin Diagrams – 20-PIN DIAGRAM FOR 20-Pin QFN (4x4) RA3/MCLR/V PP RC5/CCP1 RC4 RC3/AN7 RC6/AN8/SS 2010 Microchip Technology Inc. PIC16F/LF720/721 RA0/AN0/ICSPDAT 3 18 RA1/AN1/ICSPCLK RA2/AN2/T0CKI/INT ...
Page 6
... IOC Y — IOC Y — IOC Y — IOC Y — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 2010 Microchip Technology Inc. ...
Page 7
... Appendix A: Data Sheet Revision History......................................................................................................................................... 233 ® Appendix B: Migrating From Other PIC Devices............................................................................................................................. 233 The Microchip Web Site .................................................................................................................................................................... 241 Customer Change Notification Service ............................................................................................................................................. 241 Customer Support ............................................................................................................................................................................. 241 Reader Response ............................................................................................................................................................................. 242 Product Identification System ............................................................................................................................................................ 243 2010 Microchip Technology Inc. PIC16F/LF720/721 DS41430A-page 7 ...
Page 8
... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com DS41430A-page 8 to receive the most current information on all of our products. 2010 Microchip Technology Inc. ...
Page 9
... DEVICE OVERVIEW The PIC16F/LF720/721 devices are covered by this data sheet. They are available in 20-pin packages. Figure 1-1 shows a block diagram PIC16F/LF720/721 devices. Table 1-1 out descriptions. 2010 Microchip Technology Inc. PIC16F/LF720/721 of the shows the pin- DS41430A-page 9 ...
Page 10
... RC6 RC7 PMDATL Self read/ write Flash memory EEADDR SDI/ SCK/ SCK/ SCK/ ICSPDAT ICSPCLK SDO SDO SDO SDA SCL SDA SCL SDA SCL Synchronous Synchronous Synchronous AUSART ICSP™ Serial Port Serial Port Serial Port 2010 Microchip Technology Inc. ...
Page 11
... AN11 RX DT Legend Analog input or output, CMOS = CMOS compatible input or output Open Drain, TTL = TTL compatible input Schmitt Trigger input with CMOS levels, I XTAL = Crystal levels 2010 Microchip Technology Inc. PIC16F/LF720/721 IN OUT General purpose I/O. Individually controlled interrupt-on- TTL CMOS change ...
Page 12
... A/D Channel 8 Input. ST — Slave Select input. ST CMOS General purpose I/O. AN — A/D Channel 9 Input. — CMOS SPI Data Output. Power — Positive supply. Power — Ground supply. 2 C™ = Schmitt Trigger input with I Description High Voltage, 2010 Microchip Technology Inc. ...
Page 13
... PIC16F720/LF720 will cause a wrap-around within the first program memory space. Accessing a location above the memory boundaries for the PIC16F721/LF721 will cause a wrap-around within the first program memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h. FIGURE 2-1: ...
Page 14
... DS41430A-page 14 2.2.1 GENERAL PURPOSE REGISTER FILE The register file is organized as 128 x 8 bits in the PIC16F720/LF720, 256 x 8 bits in the PIC16F721/ LF721. Each register is accessed either directly or indirectly through the File Select Register (FSR), (Refer to Section 2.5 “Indirect Addressing, INDF and FSR Registers” ...
Page 15
... Bytes General Purpose Register 96 Bytes Accesses 70h – 7Fh 7Fh BANK 0 BANK 1 Legend: = Unimplemented data memory locations, read as ‘0’ Not a physical register. 2010 Microchip Technology Inc. PIC16F/LF720/721 (*) (*) Indirect addr. 80h 100h 81h TMR0 101h 82h PCL 102h 83h STATUS ...
Page 16
... PIC16F/LF720/721 FIGURE 2-4: PIC16F721/LF721 SPECIAL FUNCTION REGISTERS (*) Indirect addr. 00h Indirect addr. TMR0 01h OPTION_REG PCL 02h PCL STATUS 03h STATUS FSR 04h FSR PORTA 05h TRISA PORTB 06h TRISB PORTC 07h TRISC 08h 09h PCLATH 0Ah PCLATH INTCON 0Bh INTCON ...
Page 17
... These registers can be addressed from any bank. 3: Accessible only when SSPM<3:0> = 1001. 4: This bit is unimplemented and reads as ‘1’. 5: See Register 6-2. 2010 Microchip Technology Inc. PIC16F/LF720/721 Bit 5 Bit 4 Bit 3 Timer0 module Register Program Counter (PC) Least Significant Byte RP0 TO PD ...
Page 18
... IOCA1 IOCA0 --00 0000 --00 0000 — — TRMT TX9D 0000 -010 0000 -010 BRG1 BRG0 0000 0000 0000 0000 — — — — — — ADFVR1 ADFVR0 q000 --00 q000 --00 — — — — -000 ---- -000 ---- 2010 Microchip Technology Inc. ...
Page 19
... These registers can be addressed from any bank. 3: Accessible only when SSPM<3:0> = 1001. 4: This bit is unimplemented and reads as ‘1’. 5: See Register 6-2. 2010 Microchip Technology Inc. PIC16F/LF720/721 Bit 5 Bit 4 Bit 3 Bit 2 Timer0 module Register Program Counter (PC) Least Significant Byte RP0 ...
Page 20
... Microchip Technology Inc. Value on all other Resets xxxx xxxx 1111 1111 0000 0000 000q quuu uuuu uuuu ---1 -111 --11 ---- 11-- 1111 — ---0 0000 0000 000x ...
Page 21
... For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. 2010 Microchip Technology Inc. PIC16F/LF720/721 For example, CLRF STATUS will clear the upper three bits and set the Z bit ...
Page 22
... Refer to “Software Programmable R/W-1 R/W-1 R/W-1 T0SE PSA U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /4) OSC WDT Rate 128 256 1 : 128 Section 12.1.3 Prescaler”. R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 23
... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) 2010 Microchip Technology Inc. PIC16F/LF720/721 2-3. U-0 U-0 U-0 — ...
Page 24
... PAGESEL SUB_P1 ;Select page 1 CALL : : ORG SUB1_P1 : : RETURN RETLW and RETFIE RETURN, CALL OF A SUBROUTINE IN PAGE 1 FROM PAGE 0 ;(800h-FFFh) SUB1_P1 ;Call subroutine in ;page 1 (800h-FFFh) 900h ;page 1 (800h-FFFh) ;called subroutine ;page 1 (800h-FFFh) ;return to ;Call subroutine ;in page 0 ;(000h-7FFh) 2010 Microchip Technology Inc. ...
Page 25
... Direct Addressing From Opcode RP1 RP0 6 Bank Select Location Select 00h Data Memory 7Fh Bank 0 Note: For memory map detail, refer to Figures 2010 Microchip Technology Inc. PIC16F/LF720/721 EXAMPLE 2-2: MOVLW020h MOVWFFSR BANKISEL020h NEXTCLRFINDF INCFFSR BTFSSFSR,4 ;all done? GOTONEXT CONTINUE 2-6. 2-2. ...
Page 26
... PIC16F/LF720/721 NOTES: DS41430A-page 26 2010 Microchip Technology Inc. ...
Page 27
... PWRT 11-bit Ripple Counter WDTOSC Note 1: Refer to the Configuration Word Register 1 2010 Microchip Technology Inc. PIC16F/LF720/721 Most registers are not affected by a WDT wake-up since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different Reset situations, as indicated in These bits are used in software to determine the nature of the Reset ...
Page 28
... If a Status bit is not implemented, that bit will be read as ‘0’. DS41430A-page 28 Condition (2) Program STATUS Counter Register 0000h 0001 1xxx ---- --0x 0000h 000u uuuu ---- --uu 0000h 0001 0uuu ---- --uu 0000h 0000 1uuu ---- -- uuu0 0uuu ---- --uu 0000h 0001 1uuu ---- --u0 ( uuu1 0uuu ---- --uu 2010 Microchip Technology Inc. PCON Register ...
Page 29
... If these conditions are not met, the device must be held in Reset until the operating conditions are met. For additional information, refer to Application Note AN607, “Power-up Trouble Shooting” (DS00607). 2010 Microchip Technology Inc. PIC16F/LF720/721 3.3 Power-up Timer (PWRT) The Power-up Timer provides a fixed 72 ms (nominal) time out on power-up only, from POR or Brown-out Reset ...
Page 30
... Low-Power WDT OSC TABLE 3-3: WDT STATUS Conditions WDTE = 0 CLRWDT Command Exit Sleep + System Clock = INTOSC, EXTCLK DS41430A-page 30 From TMR0 Clock Source 0 Postscaler Divide by 1 512 PSA 0 To T1G WDTE 2010 Microchip Technology Inc. 8 PS<2:0> TO TMR0 1 WDT Reset WDT Cleared ...
Page 31
... Power-up Timer will execute a BOR 64 ms Reset. FIGURE 3-3: BROWN-OUT SITUATIONS V DD Internal Reset V DD Internal Reset V DD Internal Reset Note delay only if PWRTE bit is programmed to ‘0’. 2010 Microchip Technology Inc. PIC16F/LF720/721 can be for more BOR DD ( & BOR V BOR ...
Page 32
... Brown-out Reset PWRTE = 1 PWRTE = 0 — T PWRT Condition Power-on Reset Brown-out Reset WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during Sleep T PWRT may have DD Section 3.5 “Brown-Out Wake-up from Sleep PWRTE = 1 — — T OST 2010 Microchip Technology Inc. ...
Page 33
... FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE MCLR Internal POR PWRT Time-out Internal Reset FIGURE 3-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH MCLR Internal POR PWRT Time-out Internal Reset 2010 Microchip Technology Inc. PIC16F/LF720/721 T PWRT T OST DD T PWRT T OST ): CASE 3 DS41430A-page 33 ...
Page 34
... Microchip Technology Inc. ...
Page 35
... When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 4: See Table 3-8 for Reset value for specific condition Reset was due to brown-out, then bit All other Resets will cause bit 2010 Microchip Technology Inc. PIC16F/LF720/721 MCLR Reset/ (1) WDT Reset (1,5) ---- --uu uuuu uxuu ...
Page 36
... uuu1 0uuu = unimplemented bit, reads as ‘0’. - Bit 4 Bit 3 Bit 2 Bit 1 Bit — — — POR BOR PCON Register ---- --0x ---- --uu ---- --uu ---- --uu ---- --uu ---- --10 ---- --uu Value on Value on all other POR, BOR (1) Resets C 0001 1xxx 000q quuu ---- --qq ---- --uu 2010 Microchip Technology Inc. ...
Page 37
... TMR1GIE IOC-RA3 IOCA3 IOC-RA4 IOCA4 IOC-RA5 IOCA5 2010 Microchip Technology Inc. PIC16F/LF720/721 The PIC16F/LF720/721 device family has 12 interrupt sources, differentiated by corresponding interrupt enable and flag bits: • Timer0 Overflow Interrupt • External Edge Detect on INT Pin Interrupt • PORTA and PORTB Change Interrupt • ...
Page 38
... See for timing details (1) (2) Interrupt Latency Inst ( — Dummy Cycle Dummy Cycle Inst (PC) . Synchronous latency = where Section 23.0 “Electrical Figure 4 0004h 0005h Inst (0004h) Inst (0005h) Inst (0004h) = instruction cycle time. Latency CY Specifications”. 2010 Microchip Technology Inc. ...
Page 39
... MOVWFSTATUS ;Move W into STATUS register SWAPFW_TEMP,F ;Swap W_TEMP SWAPFW_TEMP,W ;Swap W_TEMP into W 2010 Microchip Technology Inc. PIC16F/LF720/721 following the ISR from using invalid data. Examples of key registers include the W, STATUS, FSR and PCLATH registers. Note: The microcontroller does not normally require saving the PCLATH register ...
Page 40
... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. R/W-0 R/W-0 R/W-0 (1) (2) INTE RABIE TMR0IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) R/W-0 R/W-x INTF RABIF bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 41
... Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt 2010 Microchip Technology Inc. PIC16F/LF720/721 Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. ...
Page 42
... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. R-0 R/W-0 R/W-0 TXIF SSPIF CCP1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2010 Microchip Technology Inc. R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown ...
Page 43
... RABPU INTEDG PIE1 TMR1GIE ADIE PIR1 TMR1GIF ADIF Legend Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Capture, Compare and PWM. 2010 Microchip Technology Inc. PIC16F/LF720/721 Bit 5 Bit 4 Bit 3 Bit 2 INTE RABIE TMR0IF T0CS T0SE ...
Page 44
... PIC16F/LF720/721 NOTES: DS41430A-page 44 2010 Microchip Technology Inc. ...
Page 45
... In order to continue to support 5.0V designs, a LDO voltage regulator is integrated on the die. The LDO voltage regulator allows for the internal digital logic to operate at 3.2V, while I/O’s operate at 5. 2010 Microchip Technology Inc. PIC16F/LF720/721 from the ). DS41430A-page 45 ...
Page 46
... PIC16F/LF720/721 NOTES: DS41430A-page 46 2010 Microchip Technology Inc. ...
Page 47
... MOVLW 0Ch ;Set RA<3:2> as inputs MOVWF TRISA ;and set RA<5:4,1:0> ;as outputs 2010 Microchip Technology Inc. PIC16F/LF720/721 6.1.1 WEAK PULL-UPS Each of the PORTA pins has an individually configurable internal weak pull-up. Control bits WPUA<5:0> enable or disable each pull-up (see Register 6-5). Each weak pull-up is automatically turned off when the port pin is configured as an output ...
Page 48
... R/W-1 (2) WPUA4 WPUA3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ( ) 1 R/W-x R/W-x RA2 RA1 RA0 bit Bit is unknown R/W-1 R/W-1 TRISA1 TRISA0 bit Bit is unknown R/W-1 R/W-1 R/W-1 WPUA2 WPUA1 WPUA0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 49
... Setting a pin to an analog input automatically disables the digital input circuitry. Weak pull-ups, if available, are unaffected. The corresponding TRIS bit must be set to Input mode by the user in order to allow external control of the voltage on the pin. 2010 Microchip Technology Inc. PIC16F/LF720/721 R/W-0 ...
Page 50
... ADC • Timer1 gate input • clock output 6.1.4.6 RA5/T1CKI/CLKIN Figure 6-6 shows the diagram for this pin. This pin is configurable to function as one of the following: • a general purpose I/O • Timer1 Clock input • clock input 2010 Microchip Technology Inc. ...
Page 51
... WPUA RD WPUA PORTA TRISA RD TRISA RD PORTA IOCA RD IOCA Interrupt-on-Change ICSPDAT Note 1: ANSEL determines Analog Input mode. 2010 Microchip Technology Inc. PIC16F/LF720/721 (1) Analog Input mode RABPU PORT_ICDDAT TRIS_ICDDAT (1) Analog Input mode PORTA To A/D Converter V DD Weak V DD I/O Pin V SS DS41430A-page 51 ...
Page 52
... WR WPUA RD WPUA PORTA TRISA RD TRISA RD PORTA IOCA RD IOCA Interrupt-on-Change To A/D Converter ICSPCLK Note 1: ANSEL determines Analog Input mode. DS41430A-page 52 ICSP™ mode (1) Analog Input mode DEBUG Weak RABPU PORT_ICDCLK I/O Pin (1) Analog Input mode TRIS_ICDCLK PORTA 2010 Microchip Technology Inc. ...
Page 53
... WPUA RD WPUA D WR PORTA D WR TRISA RD TRISA RD PORTA D WR IOCA RD IOCA Interrupt-on- Change To Timer0 To INT To A/D Converter Note 1: ANSEL determines Analog Input mode. 2010 Microchip Technology Inc. PIC16F/LF720/721 (1) Analog Input mode Weak To Voltage Regulator RABPU (for PIC16F720/721 only I/O Pin ...
Page 54
... Note 1: With CLKOUT option. 2: ANSEL determines Analog Input mode. BLOCK DIAGRAM OF RA4 (2) Analog Input mode CLK modes Weak RABPU V DD CLKOUT Enable F /4 OSC I/O Pin Q CLKOUT Enable INTOSC/ (1) RC/EC Q CLKOUT Enable Analog Input mode PORTA 2010 Microchip Technology Inc. ...
Page 55
... OPTION_REG RABPU INTEDG T0CS PORTA RA5 — — TRISA TRISA5 — — Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. 2010 Microchip Technology Inc. PIC16F/LF720/721 V DD Weak V DD I/O Pin Bit 4 Bit 3 Bit 2 ...
Page 56
... RABIF flag will always be set. If multiple PORTB pins are configured for the interrupt-on-change, the user may not be able to identify which pin changed state. (Register 6-10) is used to executing read-modify-write Register 6-8). Each weak pull- The interrupt-on-change feature is 2010 Microchip Technology Inc. ...
Page 57
... Unimplemented: Read as ‘0’ Note 1: Global RABPU bit of the OPTION register must be cleared for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in configured as an output. 2010 Microchip Technology Inc. PIC16F/LF720/721 R/W-x U-0 U-0 RB4 — ...
Page 58
... Bit is cleared (1) R/W-1 U-0 U-0 ANSB4 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) . Digital input buffer disabled. U-0 U-0 — — bit Bit is unknown U-0 U-0 — — bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 59
... The RB7 pin is configurable to function as one of the following: • General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. • USART asynchronous transmit • USART synchronous clock 2010 Microchip Technology Inc. PIC16F/LF720/721 FIGURE 6-7: BLOCK DIAGRAM OF RB4 (1) Analog ...
Page 60
... ANSEL determines Analog Input mode. DS41430A-page 60 FIGURE 6-9: Data Bus WPUB Weak RD WPUB PORTB D I/O Pin WR CK TRISB TRISB RD PORTB IOCB RD Q3 IOCB ST Interrupt-on- Change To SSP BLOCK DIAGRAM OF RB6 Weak RABPU SSPEN SSP Clock I/O Pin From Q SSP PORTB 2010 Microchip Technology Inc. ...
Page 61
... TRISB7 TRISB6 TRISB5 WPUB WPUB7 WPUB6 WPUB5 RCSTA SPEN RX9 SREN TXREG RCREG Legend unknown unchanged unimplemented locations read as ‘0’. Shaded cells are not used by PORTB. 2010 Microchip Technology Inc. PIC16F/LF720/721 V DD Weak V DD I/O Pin Bit 4 Bit 3 Bit 2 ...
Page 62
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (Register 6-12) controls the PORTC INITIALIZING PORTC ; ;Init PORTC ; ;Set RC<3:2> as inputs ;and set RC<7:4,1:0> ;as outputs (Register 6-13) is used to executing read-modify-write R/W-x R/W-x R/W-x RC2 RC1 RC0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 63
... Note 1: Setting a pin to an analog input automatically disables the digital input circuitry. Weak pull-ups, if available, are unaffected. The corresponding TRIS bit must be set to Input mode by the user in order to allow external control of the voltage on the pin. 2010 Microchip Technology Inc. PIC16F/LF720/721 R/W-1 ...
Page 64
... To A/D Converter Note 1: ANSEL determines Analog Input mode. FIGURE 6-12: BLOCK DIAGRAM OF RC2 AND RC3 Data Bus PORTC TRISC Analog Input (1) mode RD TRISC RD PORTC To A/D Converter Note 1: ANSEL determines Analog Input mode. 2010 Microchip Technology Inc I/O Pin I/O Pin V SS ...
Page 65
... RD PORTC FIGURE 6-14: BLOCK DIAGRAM OF RC5 Data bus CCP1OUT Enable CCP1OUT 1 0 PORTC TRISC RD TRISC RD PORTC To CCP1 input 2010 Microchip Technology Inc. PIC16F/LF720/721 FIGURE 6-15: Data Bus I/O Pin Q PORTC TRISC RD TRISC RD PORTC To SS Input To A/D Converter Note 1: ANSEL determines Analog Input mode. ...
Page 66
... CCP1M2 CCP1M1 Value on Value on all Bit 1 Bit 0 POR, other BOR Resets TRISC0 1111 1111 1111 1111 xxxx xxxx uuuu uuuu RC1 RC0 ANSC0 11-- 1111 11-- 1111 ADON --00 0000 --00 0000 SSPM0 0000 0000 0000 0000 CCP1M0 --00 0000 --00 0000 2010 Microchip Technology Inc. ...
Page 67
... MFINTOSC 500 kHz 0 32x 1 PLL PLLEN (Configuration Word 1) 2010 Microchip Technology Inc. PIC16F/LF720/721 Clock source modes are configured by the FOSC bits in Configuration Word 1 (CONFIG1). The oscillator module can be configured for one of eight modes of operation – CLKOUT function on RA4/CLKOUT pin, CLKIN on RA5/CLKIN. ...
Page 68
... IRCF bits takes effect. This is because the old and new frequencies are derived from INTOSC via the postscaler and multiplexer. Start-up delay specifications are located in the Table 23-2 in Specifications”. for more Figure 7-1). The Section 23.0 “Electrical 2010 Microchip Technology Inc. ...
Page 69
... ICSS: Internal Clock Oscillator Status Stable bit (0.5% Stable MHz/500 kHz internal oscillator has stabilized to its maximum accuracy MHz/500 kHz internal oscillator has not yet reached its maximum accuracy bit 1-0 Unimplemented: Read as ‘0’ 2010 Microchip Technology Inc. PIC16F/LF720/721 (Figure 7-1) clock. ...
Page 70
... Oscillator module is running at the factory-calibrated frequency. 11 1111 = • • • 10 0000 = Minimum frequency DS41430A-page 70 R/W-0 R/W-0 R/W-0 TUN4 TUN3 TUN2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 TUN1 TUN0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 71
... TUN5 Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators. Note 1: See Configuration Word 1 (Register 8-1) for operation of all bits. 2010 Microchip Technology Inc. PIC16F/LF720/721 shows the ® MCU Bit 4 Bit 3 Bit 2 ...
Page 72
... PIC16F/LF720/721 NOTES: DS41430A-page 72 2010 Microchip Technology Inc. ...
Page 73
... Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 register at 2007h and Configuration Word 2 register at 2008h. These registers are only accessible during programming. 2010 Microchip Technology Inc. PIC16F/LF720/721 DS41430A-page 73 ...
Page 74
... U-1 (1) PLLEN — R/P-1 R/P-1 PWRTE WDTEN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Pin Function Select bit U-1 R/P-1 R/P-1 — BOREN1 BOREN0 bit 8 U-1 R/P-1 R/P-1 — FOSC1 FOSC0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 75
... Flash memory: PIC16F723/LF723 Write protection off 10 = 000h to 1FFh write-protected, 200h to FFFh may be modified by EECON control 01 = 000h to 7FFh write-protected, 800h to FFFh may be modified by EECON control 00 = 000h to FFFh write-protected, no addresses may be modified by EECON control 2010 Microchip Technology Inc. PIC16F/LF720/721 U-1 U-1 U-1 — ...
Page 76
... Program/Verify mode. Only the Least Significant 7 bits of the ID locations are ® reported when using MPLAB IDE. “PIC16F72X/PIC16LF72X Memory Specification” (DS41332) for more information. DS41430A-page 76 not been Specification” See the Programming 2010 Microchip Technology Inc. ...
Page 77
... ADC BLOCK DIAGRAM AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 Temperature Indicator FV REF CHS<3:0> 2010 Microchip Technology Inc. PIC16F/LF720/721 (ADC) allows shows the AV DD 0000 0001 0010 0011 0100 0101 0110 0111 ADC 1000 GO/DONE ...
Page 78
... RC clock frequency, which may ) OSC 4 MHz 1 MHz 2.0 s (2) 500 ns 1.0 s 4.0 s 2.0 s 8 s (5) 4.0 s 16.0 s (5) 8 s (5) 32.0 s (3) 16.0 s (5) 64.0 s (3) 1.0-6.0 s 1.0-6.0 s (1,4) (1,4) 2010 Microchip Technology Inc. ...
Page 79
... GIE and PEIE bits of the INTCON register must be disabled. If the GIE and PEIE bits of the INTCON register are enabled, execution will switch to the Interrupt Service Routine. Please refer to Section 9.1.4 “Interrupts” information. 2010 Microchip Technology Inc. PIC16F/LF720/721 CYCLES ...
Page 80
... MOVLW B’00000001’;AN0, On MOVWF ADCON0 CALL SampleTime ;Acquisiton delay BSF ADCON0,GO BTFSC ADCON0,GO GOTO $-1 BANKSEL ADRES MOVF ADRES,W MOVWF RESULT 2010 Microchip Technology Inc. ( reference ;Set RA0 to input ; ;Set RA0 to analog ; ; ;Start conversion ;Is conversion done? ;No, test again ; ;Read result ...
Page 81
... ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Note 1: See Section 11.0 “Temperature Indicator Module” 2: See Section 10.0 “Fixed Voltage Reference” 2010 Microchip Technology Inc. PIC16F/LF720/721 R/W-0 R/W-0 R/W-0 CHS2 CHS1 CHS0 U = Unimplemented bit, read as ‘0’ ...
Page 82
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-x R/W-x R/W-x ADRES4 ADRES3 ADRES2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit Bit is unknown R/W-x R/W-x ADRES1 ADRES0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 83
... ACQ = 5.5µs 2010 Microchip Technology Inc. PIC16F/LF720/721 selected (or changed), an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, used. This equation assumes that 1/2 LSb error is used (256 steps for the ADC). The 1/2 LSb error is the ...
Page 84
... HOLD V DD Sampling Switch 0. Rss R IC (1) I LEAKAGE 0. Full-Scale Range 1 LSB ideal Full-Scale Transition Analog Input Voltage 1 LSB ideal Zero-Scale V REF Transition HOLD Sampling Switch, Typical (k) 2010 Microchip Technology Inc. ...
Page 85
... TRISA — — TRISA5 TRISB TRISB7 TRISB6 TRISB5 TRISC TRISC7 TRISC6 TRISC5 Legend unknown unchanged, — = unimplemented read as ‘0’, module. 2010 Microchip Technology Inc. PIC16F/LF720/721 Bit 4 Bit 3 Bit 2 Bit 1 CHS2 CHS1 CHS0 GO/DONE ADCS0 — — — ANSA4 — ...
Page 86
... PIC16F/LF720/721 NOTES: DS41430A-page 86 2010 Microchip Technology Inc. ...
Page 87
... Bit 6 Bit 5 FVRCON FVRRDY FVREN TSEN Legend unknown unchanged, — = unimplemented read as ‘0’ value depends on condition. Shaded cells are not used for ADC module. 2010 Microchip Technology Inc. PIC16F/LF720/721 10-1. R/W-0 U-0 U-0 TSRNG — — Unimplemented bit, read as ‘0’ ...
Page 88
... PIC16F/LF720/721 NOTES: DS41430A-page 88 2010 Microchip Technology Inc. ...
Page 89
... The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation. 2010 Microchip Technology Inc. PIC16F/LF720/721 FIGURE 11-1: 11.2 Minimum Operating V ...
Page 90
... PIC16F/LF720/721 NOTES: DS41430A-page 90 2010 Microchip Technology Inc. ...
Page 91
... T0CS T0SE T1GSS = 11 TMR1GE WDTE Low-Power WDT OSC 2010 Microchip Technology Inc. PIC16F/LF720/721 12.1.1 8-BIT TIMER MODE The Timer0 module will increment every instruction cycle, if used without a prescaler. 8-Bit Timer mode is selected by clearing the T0CS bit of the OPTION register. When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write ...
Page 92
... T0CKI pin must be synchronized to the instruction clock. Synchronization can be accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the instruction clock. The high and low periods of the external clocking source must meet the timing requirements as shown in Section 23.0 “Electrical Specifications”. 2010 Microchip Technology Inc. ...
Page 93
... T0CS TMR0 TRISA — — TRISA5 Legend: – = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Timer0 module. 2010 Microchip Technology Inc. PIC16F/LF720/721 R/W-1 R/W-1 R/W-1 T0SE PSA U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 94
... PIC16F/LF720/721 NOTES: DS41430A-page 94 2010 Microchip Technology Inc. ...
Page 95
... Overflow T1CKI Note 1: ST buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 2010 Microchip Technology Inc. PIC16F/LF720/721 • Gate Toggle Mode • Gate Single-pulse Mode • Gate Value Status • Gate Event Interrupt Figure 13 block diagram of the Timer1 module ...
Page 96
... Operation •Write to TMR1H or TMR1L •Timer1 is disabled •Timer1 is disabled (TMR1ON = 0) when T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI is low. System Clock ( OSC Instruction Clock (F 0 OSC External Clocking on T1CKI Pin 0 Reserved 1 Table 13-2 displays Clock Source /4) 2010 Microchip Technology Inc. ...
Page 97
... A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair. 2010 Microchip Technology Inc. PIC16F/LF720/721 13.5 Timer1 Gate Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 gate circuitry ...
Page 98
... Toggle mode must be used. A specific sequence is required to put the device into the correct state to capture the next WDT counter interval. WDT Oscillator WDT Reset Enable Table 13-5. WDT Available for Wake-up T1G Source 2010 Microchip Technology Inc. ...
Page 99
... This allows the cycle times on the Timer1 gate source to be measured. See Figure 13-6 details. 2010 Microchip Technology Inc. PIC16F/LF720/721 13.5.5 TIMER1 GATE VALUE STATUS When Timer1 gate value status is utilized possible to read the most current level of the gate control value. ...
Page 100
... Timer1 can cause a Special Event Trigger to be missed. In the event that a write to TMR1H or TMR1L coincides with a Special Event Trigger from the CCP, the write will take precedence. For more information, see Section 9.2.5 “Special Event Trigger”. 2010 Microchip Technology Inc utilize OSC ...
Page 101
... FIGURE 13-3: TIMER1 GATE COUNT ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL TIMER1 N FIGURE 13-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL TIMER1 2010 Microchip Technology Inc. PIC16F/LF720/721 DS41430A-page 101 ...
Page 102
... TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL TIMER1 N Cleared by software TMR1GIF DS41430A-page 102 Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL 2010 Microchip Technology Inc. Cleared by software ...
Page 103
... TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL TIMER1 N Cleared by software TMR1GIF 2010 Microchip Technology Inc. PIC16F/LF720/721 Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL Cleared by software DS41430A-page 103 ...
Page 104
... TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Clears Timer1 gate flip-flop DS41430A-page 104 R/W-0 U-0 R/W-0 T1CKPS0 — T1SYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) OSC /4) OSC ) OSC U-0 R/W-0 — TMR1ON bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 105
... T1GSS<1:0>: Timer1 Gate Source Select bits 00 = Timer1 gate pin 01 = Timer0 overflow output 10 = TMR2 match PR2 output 11 = Watchdog Timer scaler overflow Watchdog Timer oscillator is turned on if TMR1GE = 1, regardless of the state of TMR1ON 2010 Microchip Technology Inc. PIC16F/LF720/721 R/W-0 R/W-0 R-x T1GSPM T1GGO/ ...
Page 106
... TMR1IF 0000 0000 0000 0000 — xxxx ---- uuuu ---- xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu — 1111 ---- 1111 ---- TRISC0 1111 1111 1111 1111 TMR1ON 0000 -0-0 uuuu -u-u T1GSS0 0000 0x00 uuuu uxuu 2010 Microchip Technology Inc. ...
Page 107
... OSC 1:1, 1:4, 1:16 2 T2CKPS<1:0> 2010 Microchip Technology Inc. PIC16F/LF720/721 The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to 00h and the PR2 register is set to FFh. Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a ‘ ...
Page 108
... Value on Value on Bit 0 all other POR, BOR Resets RABIF 0000 000x 0000 000x TMR1IE 0000 0000 0000 0000 0000 0000 0000 0000 TMR1IF 1111 1111 1111 1111 0000 0000 0000 0000 T2CKPS0 -000 0000 -000 0000 2010 Microchip Technology Inc. ...
Page 109
... CCP1 pin is unaffected) 1011 = Compare mode, trigger special event (CCP1IF bit of the PIR1register is set, TMR1 is reset and A/D conversion is started if the ADC module is enabled. CCP1 pin is unaffected.) 11xx = PWM mode. 2010 Microchip Technology Inc. PIC16F/LF720/721 TABLE 15-1: CCP MODE – TIMER ...
Page 110
... CHANGING BETWEEN CAPTURE PRESCALERS ;Set Bank bits to point ;to CCP1CON ;Turn CCP module off ; the new prescaler ; move value and CCP ON ;Load CCP1CON with this ; value /4 external clock OSC /4, then Timer1 will not OSC Section 15.1 2010 Microchip Technology Inc. ...
Page 111
... Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TRISB TRISB7 TRISB6 TRISB5 TRISC TRISC7 TRISC6 TRISC5 Legend Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the capture. 2010 Microchip Technology Inc. PIC16F/LF720/721 Bit 4 Bit 3 Bit 2 Bit 1 ANSB4 — — — B1 ...
Page 112
... Since F OSC down during Sleep mode, the Compare mode will not function properly during Sleep. ) should not be used in Compare OSC /4) or from an OSC Interrupt mode is chosen the match condition by the Timer1 Reset, will is shut OSC 2010 Microchip Technology Inc. ...
Page 113
... Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TRISB TRISB7 TRISB6 TRISB5 TRISC TRISC7 TRISC6 TRISC5 Legend Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the compare. 2010 Microchip Technology Inc. PIC16F/LF720/721 Bit 4 Bit 3 Bit 2 Bit 1 CHS2 CHS1 CHS0 GO/DONE ANSB4 — ...
Page 114
... TRIS bit. Note: Clearing the CCP1CON register will Section 15.3.8 relinquish CCP1 control of the CCP1 pin. CCP1 TRIS ), or 2 bits of the (Figure 15-4) has a time base CCP PWM OUTPUT TMR2 = PR2 TMR2 = CCPR1L:CCP1CON<5:4> 2010 Microchip Technology Inc. ...
Page 115
... The Timer2 postscaler Section 14.1 “Timer2 Operation”) is not used in the determination of the PWM frequency. 2010 Microchip Technology Inc. PIC16F/LF720/721 15.3.3 PWM DUTY CYCLE The PWM duty cycle is specified by writing a 10-bit value to multiple registers: CCPR1L register and DC1 and B1 bits of the CCP1CON register. The CCPR1L contains the eight MSbs and the DC1 and B1 bits of the CCP1CON register contain the two LSbs ...
Page 116
... PWM signal on the first output, then step 6 may be ignored. log 4 PR2 + 1 ----------------------------------------- - bits 2 log = 20 MHz) 156.3 kHz 208.3 kHz 1 1 0x1F 0x17 7 6 MHz) 153.85 kHz 200.0 kHz 1 1 0x0C 0x09 5 5 2010 Microchip Technology Inc. ...
Page 117
... TOUTPS2 TMR2 TRISB TRISB7 TRISB6 TRISB5 TRISC TRISC7 TRISC6 TRISC5 Legend Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the PWM. 2010 Microchip Technology Inc. PIC16F/LF720/721 Bit 4 Bit 3 Bit 2 Bit 1 ANSB4 — — — B1 CCP1M3 CCP1M2 ...
Page 118
... PIC16F/LF720/721 NOTES: DS41430A-page 118 2010 Microchip Technology Inc. ...
Page 119
... Multiplier x4 SYNC 1 SPBRG BRGH x 2010 Microchip Technology Inc. PIC16F/LF720/721 The AUSART module includes the following capabilities: • Full-duplex asynchronous transmit and receive • Two-character input buffer • One-character output buffer • Programmable 8-bit or 9-bit character length Synchronous • Address detection in 9-bit mode (AUSART) • ...
Page 120
... Register 16-1 Register 16-2, respectively. DS41430A-page 120 MSb Data Stop Recovery F OSC ÷ x16 x64 FERR and CREN OERR RSR Register LSb • • • ( START RX9 FIFO RX9D RCREG Register 8 Data Bus RCIF Interrupt RCIE 2010 Microchip Technology Inc. ...
Page 121
... Setting the SPEN bit of the RCSTA register enables the AUSART and automatically configures the TX/CK I/O pin as an output. 2010 Microchip Technology Inc. PIC16F/LF720/721 Note 1: When the SPEN bit is set the RX/DT I/O pin is automatically configured as an input, ...
Page 122
... TX9D data bit. 7. Load 8-bit data into the TXREG register. This will start the transmission. bit 0 bit 1 bit 7/8 Word 1 bit 0 bit 1 bit 7/8 Word Stop bit Start bit bit 0 Stop bit Word 2 Word 2 Transmit Shift Reg. 2010 Microchip Technology Inc. ...
Page 123
... AUSART receiver. The FIFO and RSR registers are not directly accessible by software. Access to the received data is via the RCREG register. 2010 Microchip Technology Inc. PIC16F/LF720/721 Bit 4 Bit 3 Bit 2 ...
Page 124
... Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG. 2010 Microchip Technology Inc. ...
Page 125
... RCREG register overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 2010 Microchip Technology Inc. PIC16F/LF720/721 16.1.2.9 9-bit Address Detection Mode Setup This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1 ...
Page 126
... TMR1IE 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 0000 0000 0000 0000 RX9D 0000 000x 0000 000x BRG0 0000 0000 0000 0000 TRISC0 1111 1111 1111 1111 TX9D 0000 -010 0000 -010 2010 Microchip Technology Inc. ...
Page 127
... TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Synchronous mode. 2010 Microchip Technology Inc. PIC16F/LF720/721 R/W-0 U-0 R/W-0 (1) SYNC — BRGH U = Unimplemented bit, read as ‘ ...
Page 128
... Note 1: The AUSART module automatically changes the pin from tri-state to drive as needed. Configure TRISx = 1. DS41430A-page 128 R/W-0 R/W-0 R-0 CREN ADDEN FERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R-0 R-x OERR RX9D bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 129
... TXSTA CSRC TX9 TXEN Legend unknown unimplemented read as ‘0’. Shaded cells are not used for the Baud Rate Generator. 2010 Microchip Technology Inc. PIC16F/LF720/721 EXAMPLE 16-1: For a device with F 9600, and Asynchronous mode with SYNC = 0 and BRGH = 0 (as seen in ...
Page 130
... F = 11.0592 MHz OSC SPBRG SPBRG Actual % value value Rate Error (decimal) (decimal) — — — — — — — — — — — — 103 9600 0. 10473 0. 19.20k 0. 57.60k 0.00 11 — 115.2k 0.00 5 2010 Microchip Technology Inc. ...
Page 131
... Microchip Technology Inc. PIC16F/LF720/721 SYNC = 0, BRGH = 4.000 MHz F = 3.6864 MHz OSC OSC SPBRG % Actual % value Rate Error Rate Error (decimal) — — ...
Page 132
... If interrupts are desired, set the TXIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register 9-bit transmission is selected, the ninth bit should be loaded in the TX9D bit. 8. Start transmission by loading data to the TXREG register. 2010 Microchip Technology Inc. ...
Page 133
... TRISC6 TRISC5 TXREG AUSART Transmit Data Register TXSTA CSRC TX9 TXEN Legend unknown unimplemented read as ‘0’. Shaded cells are not used for synchronous master transmission. 2010 Microchip Technology Inc. PIC16F/LF720/721 bit 2 bit 7 bit 0 Word 2 bit 0 bit 2 bit 1 Bit 4 Bit 3 ...
Page 134
... Read the 8-bit received data by reading the RCREG register. 11 overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit, which resets the AUSART. 2010 Microchip Technology Inc. ...
Page 135
... RX9 SREN TRISC TRISC7 TRISC6 TRISC5 TXSTA CSRC TX9 TXEN Legend unknown unimplemented read as ‘0’. Shaded cells are not used for synchronous master reception. 2010 Microchip Technology Inc. PIC16F/LF720/721 bit 1 bit 2 bit 3 bit 4 Bit 4 Bit 3 Bit 2 Bit 1 INTE RABIE ...
Page 136
... POR, BOR Resets RABIF 0000 000x 0000 000x TMR1IE 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 RX9D 0000 000x 0000 000x TRISC0 1111 1111 1111 1111 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 2010 Microchip Technology Inc. ...
Page 137
... TXSTA CSRC TX9 TXEN Legend unknown unimplemented read as ‘0’. Shaded cells are not used for synchronous slave reception. 2010 Microchip Technology Inc. PIC16F/LF720/721 16.3.2.4 Synchronous Slave Reception Setup 1. Set the SYNC and SPEN bits and clear the CSRC bit. ...
Page 138
... TXIF flag. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the GIE, Global Interrupt Enable bit is also set then the Interrupt Service Routine at address 0004h will be called. 2010 Microchip Technology Inc. ...
Page 139
... Shift Register (SSPSR) LSb MSb General I/O Processor 1 2010 Microchip Technology Inc. PIC16F/LF720/721 A typical SPI connection between microcontroller devices is shown in than one slave device is accomplished via multiple hardware slave select lines. External hardware and additional I/O pins must be used to support multiple slave select addressing ...
Page 140
... SSPBUF Reg SSPSR Reg SDI bit 0 bit 7 Shift Clock SDO SS Control RA5/SS Enable RA0/SS SSSEL 2 Clock Select Edge Select 2 Edge Select Prescaler SCK 4 TRISx SSPM<3:0> DS41430A-page 140 Internal Data Bus Write TMR2 Output F OSC 4, 16, 64 2010 Microchip Technology Inc. ...
Page 141
... TRIS register as follows: • SDI configured as input • SDO configured as output • SCK configured as output 2010 Microchip Technology Inc. PIC16F/LF720/721 17.1.1.3 Master Mode Setup In Master mode, the data is transmitted/received as soon as the SSPBUF register is loaded with a byte ...
Page 142
... MOVWF RXDATA ;Save in user RAM, if data is meaningful MOVF TXDATA reg = contents of TXDATA MOVWF SSPBUF ;New data to xmit DS41430A-page 142 bit 2 bit 5 bit 4 bit 3 bit 1 bit 5 bit 4 bit 2 bit 1 bit 3 4 Clock Modes bit 0 bit 0 bit 0 bit 0 2010 Microchip Technology Inc. ...
Page 143
... A SPI module transmits and receives at the same time, occasionally causing dummy data to be transmitted/ received the user to determine which data used and what can be discarded. 2010 Microchip Technology Inc. PIC16F/LF720/721 17.1.2.2 Enabling Slave I/O To enable the serial port, the SSPEN bit of the SSPCON register must be set ...
Page 144
... SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS41430A-page 144 bit 6 bit 2 bit 5 bit 4 bit 3 bit 6 bit 5 bit 4 bit 2 bit 3 bit 1 bit 0 bit 0 bit 1 bit 0 bit 0 2010 Microchip Technology Inc. ...
Page 145
... SSPIF Interrupt Flag SSPSR to SSPBUF 2010 Microchip Technology Inc. PIC16F/LF720/721 When the SPI module resets, the bit counter is cleared to ‘0’. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. shows the timing waveform for such a synchronization event ...
Page 146
... When enabled, these pins must be properly configured as input or output. DS41430A-page 146 R/W-0 R/W-0 R/W-0 CKP SSPM3 SSPM2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /4 OSC /16 OSC /64 OSC R/W-0 R/W-0 SSPM1 SSPM0 bit Bit is unknown (1) 2010 Microchip Technology Inc. ...
Page 147
... UA: Update Address bit 2 Used mode only. bit 0 BF: Buffer Full Status bit 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty 2010 Microchip Technology Inc. PIC16F/LF720/721 R-0 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 148
... TMR1IF 1111 1111 1111 1111 xxxx xxxx uuuu uuuu SSPM0 0000 0000 0000 0000 BF 0000 0000 0000 0000 — 1111 ---- 1111 ---- TRISC0 1111 1111 1111 1111 T2CKPS0 -000 0000 -000 0000 2010 Microchip Technology Inc. ...
Page 149
... Clock SSPSR Reg SDA MSb LSb SSPMSK Reg Match Detect SSPADD Reg Start and Stop bit Detect 2010 Microchip Technology Inc. PIC16F/LF720/721 FIGURE 17-8: Master SDA SCL 2 C The SSP module has six registers for I They are: • SSP Control (SSPCON) register • ...
Page 150
... SSPOV. Flag bit BF is cleared by reading the SSPBUF register, while bit SSPOV is cleared through software. Generate ACK Pulse Yes Yes Stop Condition shows the results of when a data Set bit SSPIF (SSP Interrupt occurs if enabled) Yes Yes Yes Yes 2010 Microchip Technology Inc. ...
Page 151
... An ACK pulse is generated. • SSP Interrupt Flag bit, SSPIF of the PIR1 register, is set (interrupt is generated if enabled) on the falling edge of the ninth SCL pulse. 2010 Microchip Technology Inc. PIC16F/LF720/721 17.2.4.2 10-bit Addressing In 10-bit Address mode, two address bytes need to be ...
Page 152
... Receiving Address SDA SCL S SSPIF BF SSPOV DS41430A-page 152 Receiving Data ACK ACK Cleared in software SSPBUF register is read Bit SSPOV is set because the SSPBUF register is still full. Receiving Data ACK Bus Master sends Stop condition ACK is not sent. 2010 Microchip Technology Inc. ...
Page 153
... FIGURE 17-11: I C™ SLAVE MODE TIMING (RECEPTION, 10-BIT ADDRESS) 2010 Microchip Technology Inc. PIC16F/LF720/721 DS41430A-page 153 ...
Page 154
... SCL held low while CPU responds to SSPIF Cleared in software SSPBUF is written in software From SSP Interrupt to clear BF flag Set bit after writing to SSPBUF (the SSPBUF must be written to before the CKP bit can be set) Transmitting Data ACK Service Routine 2010 Microchip Technology Inc. ...
Page 155
... FIGURE 17-13 SLAVE MODE TIMING (TRANSMISSION 10-BIT ADDRESS) 2010 Microchip Technology Inc. PIC16F/LF720/721 DS41430A-page 155 ...
Page 156
... Refer to Application Note AN578, “Use of the SSP Module in the I (DS00578) for more information bus may Note AN554, “Software 2 C™ Bus Master” (DS00554) for more 2 C™ Multi-Master Environment” 2010 Microchip Technology Inc. ...
Page 157
... CLOCK SYNCHRONIZATION TIMING SDA DX SCL CKP WR SSPCON 2010 Microchip Technology Inc. PIC16F/LF720/721 17.2.11 SLEEP OPERATION While in Sleep mode, the I addresses of data, and when an address match or C master device complete byte transfer occurs, wake the processor from Sleep (if SSP interrupt is enabled). ...
Page 158
... When enabled, these pins must be properly configured as input or output using the associated TRIS bit. DS41430A-page 158 R/W-0 R/W-0 R/W-0 CKP SSPM3 SSPM2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ( MODE) R/W-0 R/W-0 SSPM1 SSPM0 bit Bit is unknown (2) 2010 Microchip Technology Inc. ...
Page 159
... Address does not need to be updated bit 0 BF: Buffer Full Status bit Receive Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty 2010 Microchip Technology Inc. PIC16F/LF720/721 R-0 R Unimplemented bit, read as ‘0’ ...
Page 160
... TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 xxxx xxxx uuuu uuuu 0000 0000 0000 0000 SSPM0 0000 0000 0000 0000 1111 1111 1111 1111 BF 0000 0000 0000 0000 — 1111 ---- 1111 ---- 2010 Microchip Technology Inc. ...
Page 161
... Store in user location MOVF PMDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location 2010 Microchip Technology Inc. PIC16F/LF720/721 18.1 Program Memory Read Operation To read a program memory location, the user must write two bytes of the address to the PMADRH and PMADRL registers, (PMCON1< ...
Page 162
... The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. PMCON2 is not a physical register. Reading PMCON2 will read all ‘0’s. The PMCON2 register is used exclusively in the Flash memory write sequence INSTR ( INSTR ( INSTR ( Executed here Executed here 2010 Microchip Technology Inc. ...
Page 163
... PMDATL and PMDATH registers. Then, the sequence of events to transfer data to the buffer registers must be executed. 2010 Microchip Technology Inc. PIC16F/LF720/721 When the LWLO bit is ‘1’, the write sequence will only load the buffer register and will not actually initiate the write to program Flash: 1 ...
Page 164
... Example 18-2. The initial address is loaded into the PMADRH:PMADRL register pair; the 32 words of data are loaded using indirect addressing. DS41430A-page 164 PMDATH PMDATL 6 14 PMADRL<4:0> = 00010 Buffer Register Buffer Register Program Memory PMADRL<4:0> = 11111 Buffer Register 2010 Microchip Technology Inc. ...
Page 165
... MOVWF PMCON2 MOVLW AAh MOVWF PMCON2 BSF PMCON1,WR NOP NOP BCF PMCON1,WREN 2010 Microchip Technology Inc. PIC16F/LF720/721 ; Bank 3 ; Load initial address ; ; ; ; Load initial data address ; ; Load initial data address ; ; Load first data byte into lower ; ; Load second data byte into upper ...
Page 166
... PMCON registers, but the protected program memory cannot be modified using ICSP mode. R/W/HC-0/0 U-0 R/W-0/0 FREE — WREN S = Setable bit, cleared in hardware U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared program memory that are R/S/HC-0/0 R/S/HC-0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 167
... R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 PMA<12:8>: Program Memory Read Address bits 2010 Microchip Technology Inc. PIC16F/LF720/721 R/W-x R/W-x R/W-x PMD12 PMD11 PMD10 U = Unimplemented bit, read as ‘0’ ...
Page 168
... Program Memory Read Data Register High Byte R/W-x R/W-x R/W-x PMA2 PMA1 PMA0 bit Bit is unknown Value on Value on all Bit 0 POR, BOR other Resets RD 1000 -000 1000 -000 ---- ---- ---- ---- ---0 0000 ---0 0000 0000 0000 0000 0000 --xx xxxx --xx xxxx xxxx xxxx xxxx xxxx 2010 Microchip Technology Inc. ...
Page 169
... The MCLR pin must logic high level when external MCLR is enabled. Note: A Reset generated by a WDT time-out does not drive MCLR pin low. 2010 Microchip Technology Inc. PIC16F/LF720/721 19.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1 ...
Page 170
... SSPIF CCP1IF TMR2IF 0004h 0005h Inst(0004h) Inst(0005h) Dummy Cycle Inst(0004h) Value on Value on all Bit 0 POR, BOR other Resets — 0000 ---- 0000 ---- RABIF 0000 000x 0000 000x TMR1IE 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 2010 Microchip Technology Inc. ...
Page 171
... GND Data Clock 2010 Microchip Technology Inc. PIC16F/LF720/721 The device is placed into Program/Verify mode by holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/V Program/Verify mode the program memory, user IDs and the Configuration Words are programmed through serial communications ...
Page 172
... PIC16F/LF720/721 NOTES: DS41430A-page 172 2010 Microchip Technology Inc. ...
Page 173
... PORTB instruction will read PORTB, clear all the data bits, then write the result back to PORTB. This example would have the unin- tended consequence of clearing the condition that set the RABIF flag. 2010 Microchip Technology Inc. PIC16F/LF720/721 TABLE 21-1: OPCODE FIELD DESCRIPTIONS ...
Page 174
... TO, PD 0000 0110 0100 1kkk kkkk kkkk Z 1000 kkkk kkkk 00xx kkkk kkkk 0000 0000 1001 01xx kkkk kkkk 0000 0000 1000 TO, PD 0000 0110 0011 C, DC, Z 110x kkkk kkkk Z 1010 kkkk kkkk 2010 Microchip Technology Inc. ...
Page 175
... Status Affected: Z Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. 2010 Microchip Technology Inc. PIC16F/LF720/721 BCF Syntax: k Operands: Operation: Status Affected: ...
Page 176
... Operands: d [0,1] ( (destination) Operation: Status Affected: Z Description: Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. 2010 Microchip Technology Inc. ...
Page 177
... Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. 2010 Microchip Technology Inc. PIC16F/LF720/721 INCFSZ Increment f, Skip if 0 Syntax: [ label ] INCFSZ f,d 0 ...
Page 178
... Move label ] MOVWF f 0 f 127 (W) (f) None Move data from W register to register ‘f’ MOVW OPTION F Before Instruction OPTION = 0xFF W = 0x4F After Instruction OPTION = 0x4F W = 0x4F No Operation [ label ] NOP None No operation None No operation NOP 2010 Microchip Technology Inc. ...
Page 179
... Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = TOS GIE = 1 2010 Microchip Technology Inc. PIC16F/LF720/721 RETLW Return with literal in W Syntax: [ label ] RETLW k 0 k 255 Operands: k (W); Operation: TOS PC Status Affected: None ...
Page 180
... SUBLW k 0 k 255 k - (W) W) The W register is subtracted (2’s complement method) from the eight-bit literal ‘k’. The result is placed in the W register. W W<3:0> k<3:0> W<3:0> k<3:0> 2010 Microchip Technology Inc. ...
Page 181
... The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed in register ‘f’. 2010 Microchip Technology Inc. PIC16F/LF720/721 XORLW Exclusive OR literal with W Syntax: [ label ] XORLW k 0 ...
Page 182
... PIC16F/LF720/721 NOTES: DS41430A-page 182 2010 Microchip Technology Inc. ...
Page 183
... MPLAB ICD 3 - PICkit™ 3 Debug Express • Device Programmers - PICkit™ 2 Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits 2010 Microchip Technology Inc. PIC16F/LF720/721 1.1 MPLAB Integrated Development Environment Software ® digital signal The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market ...
Page 184
... Support for the entire device instruction set ® standard HEX • Support for fixed-point and floating-point data • Command line interface • Rich directive set • Flexible macro language • MPLAB IDE compatibility 2010 Microchip Technology Inc. ...
Page 185
... Microchip Technology Inc. PIC16F/LF720/721 1.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Micro- ...
Page 186
... This usually includes a single application and debug capability, all for DDMAX on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. ® L security ICs, CAN ® 2010 Microchip Technology Inc. ...
Page 187
... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. 2010 Microchip Technology Inc. PIC16F/LF720/721 ........................................................................... -0. ) ...
Page 188
... V FVR DD 2.5V = 2.048V, V FVR DD 4.75V; = 4.096V, V FVR DD 85°C A 2.5V = 1.024V, V FVR DD 2.5V = 2.048V, V FVR DD 4.75V; = 4.096V, V FVR DD 125°C A Section 3.2 “Power-on Reset for details. 2010 Microchip Technology Inc. ...
Page 189
... FIGURE 23-1: POR AND POR REARM WITH SLOW RISING POR V PORR V SS NPOR V SS Note 1: When NPOR is low, the device is held in Reset. 1 s typical POR 2.7 s typical VLOW 2010 Microchip Technology Inc. PIC16F/LF720/721 DD POR REARM (3) (2) T POR T VLOW DS41430A-page 189 ...
Page 190
... F OSC HFINTOSC mode 1.5 1.85 mA 3.0 1 1.2 mA 1.8 F OSC HFINTOSC mode 1.5 1.7 mA 3.0 1.7 2.1 mA 5.0 ; MCLR = V DD Conditions Note = 1 MHz = 1 MHz = 4 MHz = 4 MHz = 500 kHz = 500 kHz = 8 MHz = 8 MHz = 16 MHz = 16 MHz ; WDT disabled. DD 2010 Microchip Technology Inc. ...
Page 191
... Sleep mode, with all I/O pins in high-impedance state and tied Fixed Voltage Reference is automatically enabled whenever the BOR is enabled. 4: A/D oscillator source 2010 Microchip Technology Inc. PIC16F/LF720/721 Standard Operating Conditions (unless otherwise stated) -40°C T Operating temperature -40°C T Standard Operating Conditions (unless otherwise stated) -40° ...
Page 192
... V V V Pin at high- SS PIN DD impedance, 85°C nA 125°C V 85°C SS PIN DD nA 125° 3.3V PIN SS 5.0V PIN 8mA 6mA 3. 1.8mA 1. 3.5mA 3mA 3. 1mA 1. E/W Temperature during programming: 10°C T 40° 2010 Microchip Technology Inc. ...
Page 193
... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Including OSC2 in CLKOUT mode. 2010 Microchip Technology Inc. PIC16F/LF720/721 Standard Operating Conditions (unless otherwise stated) Operating temperature -40° ...
Page 194
... QFN 4x4mm package C/W 28.1 20-pin PDIP package C/W 24.2 20-pin SOIC package C/W 32.2 20-pin SSOP package C/W 2.5 20-pin QFN 4x4mm package C 150 — INTERNAL — INTERNAL DD = (I — — DER MAX J 2010 Microchip Technology Inc ( ( )/ ...
Page 195
... I/O PORT mc MCLR Uppercase letters and their meanings Fall H High I Invalid (High-impedance) L Low FIGURE 23-2: LOAD CONDITIONS Load Condition Pin Legend for all pins for L OSC2 output 2010 Microchip Technology Inc. PIC16F/LF720/721 T Time osc OSC1 SCK T0CKI t1 T1CKI Period R Rise ...
Page 196
... FIGURE 23-4: PIC16F720/721 VOLTAGE FREQUENCY GRAPH, -40°C 5.5 3.6 2.5 2.3 2.0 1 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. DS41430A-page 196 OS02 OS04 OS04 OS03 10 16 Frequency (MHz T +125°C A 2010 Microchip Technology Inc. ...
Page 197
... FIGURE 23-6: HFINTOSC FREQUENCY ACCURACY OVER DEVICE V 125 -20 -40 1.8 2.0 2.5 Note 1: This chart covers both regulator enabled and regulator disabled states. 2: Regulator Nominal voltage. 2010 Microchip Technology Inc. PIC16F/LF720/721 10 16 Frequency (MHz ± 3% ± (2) 3.3 3.5 4.0 4.5 3 ...
Page 198
... V DD MHz -40°C T +125°C, — A 2. 0°C T +85°C, — kHz A 2. +60°C T +85°C, — kHz A 2. -40°C T +125°C, — kHz A 2. s 8 2010 Microchip Technology Inc. ...
Page 199
... These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25C unless otherwise stated. Note 1: Measurements are taken in RC mode where CLKOUT output Includes OSC2 in CLKOUT mode. 2010 Microchip Technology Inc. PIC16F/LF720/721 Fetch Read Q1 Q2 ...
Page 200
... BROWN-OUT RESET TIMING AND CHARACTERISTICS BOR (Device in Brown-out Reset) TBORREJ Reset (due to BOR) Note delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’. 2ms delay if PWRTE = 0 and VREGEN = 1. DS41430A-page 200 BOR HYST (Device not in Brown-out Reset) 37 (1) 33 2010 Microchip Technology Inc. ...