PIC16F721-E/SO Microchip Technology, PIC16F721-E/SO Datasheet - Page 138

• Manufacturer Part Number: PIC16F721-E/SO
• Description: 7 KB FLASH, 256 B SRAM, 18 I/O 20 SOIC .300in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F721-E/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F/LF720/721
16.4
The AUSART will remain active during Sleep only in the
Synchronous Slave mode. All other modes require the
system clock and therefore cannot generate the
necessary signals to run the Transmit or Receive Shift
registers during Sleep.
Synchronous Slave mode uses an externally generated
clock to run the Transmit and Receive Shift registers.
16.4.1
To receive during Sleep, all the following conditions
must be met before entering Sleep mode:
• RCSTA and TXSTA Control registers must be
• If interrupts are desired, set the RCIE bit of the
• The RCIF interrupt flag must be cleared by
Upon entering Sleep mode, the device will be ready to
accept data and clocks on the RX/DT and TX/CK pins,
respectively. When the data word has been completely
clocked in by the external device, the RCIF interrupt
flag bit of the PIR1 register will be set. Thereby, waking
the processor from Sleep.
Upon waking from Sleep, the instruction following the
SLEEP instruction will be executed. If the GIE, Global
Interrupt Enable bit of the INTCON register is also set,
then the Interrupt Service Routine at address 0004h
will be called.
DS41430A-page 138
configured for synchronous slave reception (refer
to
Reception
PIE1 register and the PEIE bit of the INTCON
register.
reading RCREG to unload any pending
characters in the receive buffer.
Section 16.3.2.4 “Synchronous Slave
AUSART Operation During Sleep
SYNCHRONOUS RECEIVE DURING
SLEEP
Setup”).
16.4.2
To transmit during Sleep, all the following conditions
must be met before entering Sleep mode:
• RCSTA and TXSTA Control registers must be
• The TXIF interrupt flag must be cleared by writing
• If interrupts are desired, set the TXIE bit of the
Upon entering Sleep mode, the device will be ready to
accept clocks on the TX/CK pin and transmit data on
the RX/DT pin. When the data word in the TSR has
been completely clocked out by the external device, the
pending byte in the TXREG will transfer to the TSR and
the TXIF flag will be set. Thereby, waking the processor
from Sleep. At this point, the TXREG is available to
accept another character for transmission, which will
clear the TXIF flag.
Upon waking from Sleep, the instruction following the
SLEEP instruction will be executed. If the GIE, Global
Interrupt Enable bit is also set then the Interrupt
Service Routine at address 0004h will be called.
configured for synchronous slave transmission
(refer to
Transmission
the output data to the TXREG, thereby filling the
TSR and transmit buffer.
PIE1 register and the PEIE bit of the INTCON
register.
Section 16.3.2.2 “Synchronous Slave
SYNCHRONOUS TRANSMIT
DURING SLEEP
Setup”).
 2010 Microchip Technology Inc.