PIC16F721-E/SO Microchip Technology, PIC16F721-E/SO Datasheet - Page 114

• Manufacturer Part Number: PIC16F721-E/SO
• Description: 7 KB FLASH, 256 B SRAM, 18 I/O 20 SOIC .300in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F721-E/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F/LF720/721
15.3
The PWM mode generates a Pulse-Width Modulated
signal on the CCP1 pin. The duty cycle, period and
resolution are determined by the following registers:
• PR2
• T2CON
• CCPR1L
• CCP1CON
In Pulse-Width Modulation (PWM) mode, the CCP
module produces up to a 10-bit resolution PWM output
on the CCP1 pin.
Figure 15-3
operation.
Figure 15-4
signal.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, refer to
“Setup for PWM
FIGURE 15-3:
DS41430A-page 114
Note
CCPR1H
Duty Cycle Registers
Comparator
1:
2:
CCPR1L
PWM Mode
PR2
TMR2
Comparator
The 8-bit timer TMR2 register is concatenated with
the 2-bit internal system clock (F
prescaler, to create the 10-bit time base.
In PWM mode, CCPR1H is a read-only register.
shows a simplified block diagram of PWM
(2)
shows a typical waveform of the PWM
(Slave)
Operation”.
(1)
SIMPLIFIED PWM BLOCK
DIAGRAM
Clear Timer2,
toggle CCP1 pin and
latch duty cycle
CCP1CON<5:4>
S
R
Q
OSC
Section 15.3.8
), or 2 bits of the
TRIS
CCP1
The PWM output
(period) and a time that the output stays high (duty
cycle).
FIGURE 15-4:
15.3.1
In PWM mode, the CCP1 pin is multiplexed with the
PORT data latch. The user must configure the CCP1
pin as an output by clearing the associated TRIS bit.
Note:
Pulse Width
TMR2 = 0
CCPX PIN CONFIGURATION
Clearing the CCP1CON register will
relinquish CCP1 control of the CCP1 pin.
Period
(Figure
CCP PWM OUTPUT
TMR2 = CCPR1L:CCP1CON<5:4>
 2010 Microchip Technology Inc.
15-4) has a time base
TMR2 = PR2