PIC16F721-E/SO Microchip Technology, PIC16F721-E/SO Datasheet - Page 110

• Manufacturer Part Number: PIC16F721-E/SO
• Description: 7 KB FLASH, 256 B SRAM, 18 I/O 20 SOIC .300in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F721-E/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F/LF720/721
15.1
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin CCP1. An event is defined as one of the
following and is configured by the CCP1M<3:0> bits of
the CCP1CON register:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
When a capture is made, the Interrupt Request Flag bit
CCP1IF of the PIR1 register is set. The interrupt flag
must be cleared in software. If another capture occurs
before the value in the CCPR1H, CCPR1L register pair
is read, the old captured value is overwritten by the new
captured value (refer to
15.1.1
In Capture mode, the CCP1 pin should be configured
as an input by setting the associated TRIS control bit.
FIGURE 15-1:
15.1.2
Timer1 must be running in Timer mode or Synchronized
Counter mode for the CCP module to use the capture
feature. In Asynchronous Counter mode or when
Timer1 is clocked at F
not work.
DS41430A-page 110
CCP1
Note:
Note:
System Clock (F
Capture Mode
Edge Detect
CCP1 PIN CONFIGURATION
If the CCP1 pin is configured as an output,
a write to the port can cause a capture
condition.
Prescaler
 1, 4, 16
TIMER1 MODE SELECTION
Clocking Timer1 from the system clock
(F
mode. In order for Capture mode to
recognize the trigger event on the CCP1
pin, Timer1 must be clocked from the
Instruction Clock (F
external clock source.
and
OSC
CCP1CON<3:0>
OSC
) should not be used in Capture
)
Set Flag bit CCP1IF
(PIR1 register)
OSC
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
Figure
, the capture operation may
Capture
Enable
15-1).
OSC
CCPR1H
TMR1H
/4) or from an
CCPR1L
TMR1L
15.1.3
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCP1IE interrupt enable bit of the PIE1 register clear to
avoid false interrupts. Additionally, the user should
clear the CCP1IF interrupt flag bit of the PIR1 register
following any change in operating mode
15.1.4
There are four prescaler settings specified by the
CCP1M<3:0>
Whenever the CCP module is turned off, or the CCP
module is not in Capture mode, the prescaler counter
is cleared. Any Reset will clear the prescaler counter.
Switching from one capture prescaler to another does not
clear the prescaler and may generate a false interrupt. To
avoid this unexpected operation, turn the module off by
clearing the CCP1CON register before changing the
prescaler (refer to
EXAMPLE 15-1:
15.1.5
Capture mode depends upon the Timer1 module for
proper operation. There are two options for driving the
Timer1 module in Capture mode. It can be driven by the
instruction clock (F
source.
If Timer1 is clocked by F
increment during Sleep. When the device wakes from
Sleep, Timer1 will continue from its previous state.
If Timer1 is clocked by an external clock source, then
Capture mode will operate as defined in
“Capture
BANKSEL CCP1CON
CLRF
MOVLW
MOVWF
CCP1CON
NEW_CAPT_PS ;Load the W reg with
CCP1CON
Mode”.
SOFTWARE INTERRUPT
CCP PRESCALER
CAPTURE DURING SLEEP
bits
Example
OSC
of
CHANGING BETWEEN
CAPTURE PRESCALERS
;Set Bank bits to point
;to CCP1CON
;Turn CCP module off
; the new prescaler
; move value and CCP ON
;Load CCP1CON with this
; value
 2010 Microchip Technology Inc.
/4), or by an external clock
OSC
the
15-1).
/4, then Timer1 will not
CCP1CON
Section 15.1
register.