PIC18F23K20-E/SS Microchip Technology, PIC18F23K20-E/SS Datasheet - Page 126
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PIC18F23K20-E/SS
Manufacturer Part Number
PIC18F23K20-E/SS
Description
8 KB Enh Flash, 768 RAM, 25 I/O Pb Free, Nanowatt XLP 28 SSOP .209in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F25K20T-ISS.pdf
(42 pages)
2.PIC18F25K20T-ISS.pdf
(456 pages)
3.PIC18F23K20-ISS.pdf
(10 pages)
Specifications of PIC18F23K20-E/SS
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC18F2XK20/4XK20
TABLE 10-3:
TABLE 10-4:
DS41303G-page 126
PORTB
LATB
TRISB
WPUB
IOCB
SLRCON
INTCON
INTCON2
INTCON3
ANSELH
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB.
Note 1:
RB6/KBI2/PGC
RB7/KBI3/PGD
Legend:
Note 1:
Name
2:
3:
Pin
Not implemented on PIC18F2XK20 devices.
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Configuration on POR is determined by the PBADEN Configuration bit. Pins are configured as analog inputs by default
when PBADEN is set and digital inputs when PBADEN is cleared.
Alternate assignment for CCP2 when the CCP2MX Configuration bit is ‘0’. Default assignment is RC1.
All other pin functions are disabled when ICSP or ICD are enabled.
PORTB Data Latch Register (Read and Write to Data Latch)
PORTB Data Direction Control Register
GIE/GIEH PEIE/GIEL TMR0IE
WPUB7
INT2IP
IOCB7
RBPU
Bit 7
PORTB I/O SUMMARY (CONTINUED)
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
RB7
—
—
Function
KBI2
PGC
KBI3
PGD
RB6
RB7
INTEDG0 INTEDG1 INTEDG2
WPUB6
IOCB6
INT1IP
Bit 6
RB6
Setting
—
—
TRIS
0
1
1
x
0
1
1
x
x
WPUB5
I/O
IOCB5
O
O
O
I
I
I
I
I
I
Bit 5
RB5
—
—
—
Type
DIG
TTL
TTL
DIG
TTL
TTL
DIG
I/O
ST
ST
SLRE
WPUB4
INT0IE
INT2IE
ANS12
IOCB4
Bit 4
RB4
LATB<6> data output.
PORTB<6> data input; Programmable weak pull-up.
Interrupt-on-pin change.
Serial execution (ICSP) clock input for ICSP and ICD operation.
LATB<7> data output.
PORTB<7> data input; Programmable weak pull-up.
Interrupt-on-pin change.
Serial execution data output for ICSP and ICD operation.
Serial execution data input for ICSP and ICD operation.
(1)
SLRD
WPUB3
INT1IE
ANS11
RBIE
Bit 3
RB3
—
—
(1)
TMR0IF
TMR0IP
WPUB2
ANS10
SLRC
Bit 2
RB2
—
—
Description
WPUB1
INT0IF
INT2IF
SLRB
ANS9
2010 Microchip Technology Inc.
Bit 1
RB1
—
—
WPUB0
INT1IF
SLRA
ANS8
RBIF
RBIP
Bit 0
RB0
—
(3)
(3)
on page
Values
Reset
(3)
62
62
62
62
62
63
59
59
59
62
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