PIC18F23K20-E/SS Microchip Technology, PIC18F23K20-E/SS Datasheet - Page 193
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PIC18F23K20-E/SS
Manufacturer Part Number
PIC18F23K20-E/SS
Description
8 KB Enh Flash, 768 RAM, 25 I/O Pb Free, Nanowatt XLP 28 SSOP .209in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F25K20T-ISS.pdf
(42 pages)
2.PIC18F25K20T-ISS.pdf
(456 pages)
3.PIC18F23K20-ISS.pdf
(10 pages)
Specifications of PIC18F23K20-E/SS
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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17.0
17.1
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I
The I
hardware:
• Master mode
• Multi-Master mode
• Slave mode
17.2
The MSSP module has seven associated registers.
These include:
• SSPSTA – STATUS register
• SSPCON1 – First Control register
• SSPCON2 – Second Control register
• SSPBUF – Transmit/Receive buffer
• SSPSR – Shift register (not directly accessible)
• SSPADD – Address register
• SSPMSK – Address Mask register
The use of these registers and their individual Configu-
ration bits differ significantly depending on whether the
MSSP module is operated in SPI or I
Additional details are provided under the individual
sections.
2010 Microchip Technology Inc.
- Full Master mode
- Slave mode (with general address call)
2
C interface supports the following modes in
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
Master SSP (MSSP) Module
Overview
Control Registers
2
C)
2
C mode.
17.3
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes
communication, typically three pins are used:
• Serial Data Out – SDO
• Serial Data In – SDI/SDA
• Serial Clock – SCK/SCL
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select – SS
Figure 17-1 shows the block diagram of the MSSP
module when operating in SPI mode.
FIGURE 17-1:
PIC18F2XK20/4XK20
SCK/SCL
SDI/SDA
SDO
SS
SPI Mode
of
SPI
Read
are
SS Control
Select
SMP:CKE
Edge
MSSP BLOCK DIAGRAM
(SPI MODE)
Select
bit 0
Edge
Enable
supported.
TRIS bit
SSPBUF Reg
Data to TX/RX in SSPSR
SSPSR Reg
2
Clock Select
SSPM<3:0>
4
DS41303G-page 193
2
To
(
Prescaler
4, 16, 64
TMR2 Output
Write
Clock
Shift
accomplish
Data Bus
Internal
2
T
OSC
)
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