PIC18F23K20-E/SS Microchip Technology, PIC18F23K20-E/SS Datasheet - Page 268
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PIC18F23K20-E/SS
Manufacturer Part Number
PIC18F23K20-E/SS
Description
8 KB Enh Flash, 768 RAM, 25 I/O Pb Free, Nanowatt XLP 28 SSOP .209in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F25K20T-ISS.pdf
(42 pages)
2.PIC18F25K20T-ISS.pdf
(456 pages)
3.PIC18F23K20-ISS.pdf
(10 pages)
Specifications of PIC18F23K20-E/SS
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC18F2XK20/4XK20
19.2
19.2.1
To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. Setting the GO/
DONE bit of the ADCON0 register to a ‘1’ will, depend-
ing on the ACQT bits of the ADCON2 register, either
immediately start the Analog-to-Digital conversion or
start an acquisition delay followed by the Analog-to-
Digital conversion.
FIGURE 19-3:
FIGURE 19-4:
DS41303G-page 268
(Holding capacitor continues
acquiring input)
Set GO bit
1
T
CY
Set GO bit
T
ADC Operation
Holding capacitor is disconnected from analog input (typically 100 ns)
ACQT
Acquisition
Automatic
- T
STARTING A CONVERSION
2
Time
AD
Conversion starts
Cycles
T
AD
3
1 T
A/D CONVERSION T
A/D CONVERSION T
AD
b9
4
2 T
(Holding capacitor is disconnected from analog input)
Conversion starts
AD
b8
1
3 T
b9
AD
2
b7
4 T
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
AD
b8
3
b6
AD
AD
5 T
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
CYCLES (A
CYCLES (A
AD
b5
b7
4
6 T
T
AD
b4
5
b6
AD
7 T
Cycles
Figure 19-3 shows the operation of the A/D converter
after the GO bit has been set and the ACQT<2:0> bits
are cleared. A conversion is started after the following
instruction to allow entry into SLEEP mode before the
conversion begins.
Figure 19-4 shows the operation of the A/D converter
after the GO bit has been set and the ACQT<2:0> bits
are set to ‘010’ which selects a 4 T
before the conversion starts.
CQT
AD
CQT
b3
b5
Note:
6
8
<2:0> = 000, T
<2:0> = 010, T
T
AD
b4
b2
7
9 T
The GO/DONE bit should not be set in the
same instruction that turns on the ADC.
Refer to Section 19.2.9 “A/D Conver-
sion Procedure”.
AD
b3
8
b1
10
T
AD
ACQ
b0
b2
9
ACQ
2010 Microchip Technology Inc.
11
2 T
= 0)
10
= 4 T
Discharge
b1
AD
AD
AD
b0
11
)
acquisition time
2 T
Discharge
AD
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