PIC24FJ16MC102-I/SO Microchip Technology, PIC24FJ16MC102-I/SO Datasheet - Page 36

• Manufacturer Part Number: PIC24FJ16MC102-I/SO
• Description: 16-bit Motor Control Family, 16 MIPS, 16KB Flash, 1KB RAM 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ16MC102-I/SO

• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 16 KB
• Data Ram Size: 1 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-28
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Featured Product: PIC24FJ/33FJ MCUs & dsPIC® DSCs
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 16 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 21
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Lead Free Status / Rohs Status: Details

TABLE 4-10:
TABLE 4-11:
SFR Name
U1MODE
U1STA
U1TXREG
U1RXREG
U1BRG
Legend:
SPI1STAT
SPI1CON1
SPI1CON2
SPI1BUF
Legend:
Name
SFR
Addr
Addr
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0240
0242
0244
0248
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0220
0222
0224
0226
0228
SFR
SFR
UART1 REGISTER MAP
SPI1 REGISTER MAP
UTXISEL1
FRMEN
SPIEN
UARTEN
Bit 15
Bit 15
—
—
—
SPIFSD
UTXINV UTXISEL0
Bit 14
Bit 14
—
—
—
—
—
FRMPOL
SPISIDL
Bit 13
USIDL
Bit 13
—
—
—
DISSCK
Bit 12
IREN
Bit 12
—
—
—
—
—
UTXBRK
RTSMD
DISSDO
Bit 11
Bit 11
—
—
—
—
UTXEN
MODE16
Bit 10
Bit 10
—
—
—
—
—
UTXBF
SPI1 Transmit and Receive Buffer Register
UEN1
Bit 9
—
—
Bit 9
SMP
—
—
Baud Rate Generator Prescaler
UEN0
TRMT
Bit 8
Bit 8
CKE
—
—
WAKE
Bit 7
URXISEL<1:0>
SSEN
Bit 7
—
—
LPBACK
SPIROV
Bit 6
Bit 6
CKP
—
ABAUD
ADDEN
MSTEN
Bit 5
Bit 5
UART Transmit Register
UART Receive Register
—
—
URXINV
RIDLE
Bit 4
Bit 4
—
—
SPRE<2:0>
BRGH
PERR
Bit 3
Bit 3
—
—
FERR
Bit 2
Bit 2
PDSEL<1:0>
—
—
FRMDLY
OERR
SPITBF
Bit 1
Bit 1
PPRE<1:0>
URXDA
STSEL
SPIRBF
Bit 0
Bit 0
—
Resets
Resets
0000
0110
xxxx
0000
0000
0000
0000
0000
0000
All
All