PIC24FJ64GA002T-I/SO Microchip Technology, PIC24FJ64GA002T-I/SO Datasheet - Page 15

• Manufacturer Part Number: PIC24FJ64GA002T-I/SO
• Description: 64KB, Flash, 8192bytes-RAM, 16MIPS, 21I/O, 16-bit Family,nanoWatt 28 SOIC .300in
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ64GA002T-I/SO

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 64KB (22K x 24)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164339 - MODULE SKT FOR PM3 28SOICDV164033 - KIT START EXPLORER 16 MPLAB ICD2
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC24FJ64GA002T-I/SOTR

3.3
As shown in Figure 3-4, entering ICSP Program/Verify
mode requires three steps:
1.
2.
3.
The programming voltage applied to MCLR is V
which
PIC24FJXXXGA0XX devices. There is no minimum
time requirement for holding at V
removed, an interval of at least P18 must elapse before
presenting the key sequence on PGDx.
FIGURE 3-4:
© 2008 Microchip Technology Inc.
MCLR
V
PGDx
PGCx
DD
MCLR is briefly driven high, then low.
A 32-bit key sequence is clocked into PGDx.
MCLR is then driven high within a specified
period of time and held.
is
Entering ICSP Mode
P6
essentially
P14
ENTERING ICSP™ MODE
P18
V
DD
V
b31
IH
0
b30
in
1
Program/Verify Entry Code = 4D434851h
IH
the
b29
. After V
0
b28
P1A
0
case
P1B
b27
IH
1
IH
of
is
...
,
b3
0
The key sequence is a specific 32-bit pattern:
‘0100 1101 0100 0011 0100 1000 0101 0001’
(more easily remembered as 4D434851h in hexa-
decimal). The device will enter Program/Verify mode only
if the sequence is valid. The Most Significant bit (MSb) of
the most significant nibble must be shifted in first.
Once the key sequence is complete, V
applied to MCLR and held at that level for as long as
Program/Verify mode is to be maintained. An interval of
at least time, P19 and P7, must elapse before present-
ing data on PGDx. Signals appearing on PGCx before
P7 has elapsed will not be interpreted as valid.
On successful entry, the program memory can be
accessed and programmed in serial fashion. While in
ICSP mode, all unused I/Os are placed in the
high-impedance state.
b2
0
PIC24FJXXXGA0XX
b1
0
V
IH
b0
1
P19
P7
DS39768D-page 15
IH
must be