PIC24FJ64GA002T-I/SO Microchip Technology, PIC24FJ64GA002T-I/SO Datasheet - Page 47

• Manufacturer Part Number: PIC24FJ64GA002T-I/SO
• Description: 64KB, Flash, 8192bytes-RAM, 16MIPS, 21I/O, 16-bit Family,nanoWatt 28 SOIC .300in
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ64GA002T-I/SO

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 64KB (22K x 24)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164339 - MODULE SKT FOR PM3 28SOICDV164033 - KIT START EXPLORER 16 MPLAB ICD2
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC24FJ64GA002T-I/SOTR

6.2
Checksums for the PIC24FJXXXGA0XX family are
16 bits in size. The checksum is calculated by summing
the following:
• Contents of code memory locations
• Contents of Configuration registers
TABLE 6-4:
© 2008 Microchip Technology Inc.
PIC24FJ16GA002
PIC24FJ16GA004
PIC24FJ32GA002
PIC24FJ32GA004
PIC24FJ48GA002
PIC24FJ48GA004
PIC24FJ64GA002
PIC24FJ64GA004
PIC24FJ64GA006
PIC24FJ64GA008
PIC24FJ64GA010
PIC24FJ96GA006
PIC24FJ96GA008
PIC24FJ96GA010
Legend:
Note:
Device
Checksum Computation
Item
SUM[a:b]
CFGB
CW1 address is last location of implemented program memory; CW2 is (last location – 2).
CHECKSUM COMPUTATION
=
=
Description
Byte sum of locations, a to b inclusive (all 3 bytes of code memory)
Configuration Block (masked),
64/80/100-Pin Devices = Byte sum of (CW1 & 0x7DDF + CW2 & 0x87E3)
28/44-Pin Devices = Byte sum of (CW1 & 0x7FDF + CW2 & 0xFFF7)
Read Code
Protection
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
CFGB + SUM(0:02BFB)
0
CFGB + SUM(0:02BFB)
0
CFGB + SUM(0:057FB)
0
CFGB + SUM(0:057FB)
0
CFGB + SUM(0:083FB)
0
CFGB + SUM(0:083FB)
0
CFGB + SUM(0:0ABFB)
0
CFGB + SUM(0:0ABFB)
0
CFGB + SUM(0:0ABFB)
0
CFGB + SUM(0:0ABFB)
0
CFGB + SUM(0:0ABFB)
0
0
0
0
CFGB + SUM(0:0FFFB)
CFGB + SUM(0:0FFFB)
CFGB + SUM(0:0FFFB)
Checksum Computation
Table 6-4 describes how to calculate the checksum for
each device. All memory locations are summed, one
byte at a time, using only their native data size. More
specifically, Configuration registers are summed by
adding the lower two bytes of these locations (the
upper byte is ignored), while code memory is summed
by adding all three bytes of code memory.
PIC24FJXXXGA0XX
Checksum
0x7CCC
0x7CCC
0x7CCC
0xBB5A
0xBB5A
0xFACC
0xFACC
0xFACC
0xFB5A
0xFB5A
Erased
0x795A
0x795A
0x375A
0x375A
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
Value
0xAAAAAA at 0x0 and Last
Checksum with
Code Address
0xF8CE
0xF8CE
0xF8CE
0x7ACE
0x7ACE
0x7ACE
0xB95C
0xB95C
0xF95C
0xF95C
DS39768D-page 47
0x775C
0x775C
0x355C
0x355C
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000