PIC24FJ64GA002T-I/SO Microchip Technology, PIC24FJ64GA002T-I/SO Datasheet - Page 49

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PIC24FJ64GA002T-I/SO

Manufacturer Part Number
PIC24FJ64GA002T-I/SO
Description
64KB, Flash, 8192bytes-RAM, 16MIPS, 21I/O, 16-bit Family,nanoWatt 28 SOIC .300in
Manufacturer
Microchip Technology
Series
PIC® 24Fr

Specifications of PIC24FJ64GA002T-I/SO

Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
64KB (22K x 24)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164339 - MODULE SKT FOR PM3 28SOICDV164033 - KIT START EXPLORER 16 MPLAB ICD2
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC24FJ64GA002T-I/SOTR
7.0
© 2008 Microchip Technology Inc.
Standard Operating Conditions
Operating Temperature: 0°C to +70°C. Programming at +25°C is recommended.
Param
D111
D112
D113
D031
D041
D080
D090
D012
D013
P1
P1A
P1B
P2
P3
P4
P4A
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
Note 1:
No.
2:
V
I
I
V
V
V
V
C
C
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Symbol
PP
DDP
AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS
PGC
PGCL
PGCH
SET
HLD
DLY
DLY
DLY
SET
HLD
DLY
DLY
DLY
DLY
DLY
DLY
R
VALID
DLY
HLD
KEY
KEY
DLY
DLY
DD
IL
IH
OL
OH
IO
F
V
“Power Requirements” for more information. (Minimum V
V
of V
1
1
1
2
2
3
4
6
7
8
9
10
11
12
1
2
3
1
2
DDCORE
DD
A
DD
must also be supplied to the AV
Supply Voltage During Programming
Programming Current on MCLR
Supply Current During Programming
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Capacitive Loading on I/O pin (PGDx)
Filter Capacitor Value on V
Serial Clock (PGCx) Period
Serial Clock (PGCx) Low Time
Serial Clock (PGCx) High Time
Input Data Setup Time to Serial Clock ↑
Input Data Hold Time from PGCx ↑
Delay Between 4-Bit Command and
Command Operand
Delay Between 4-Bit Command Operand
and Next 4-Bit Command
Delay Between Last PGCx ↓ of Command
Byte to First PGCx ↑ of Read of Data Word
V
Input Data Hold Time from MCLR ↑
Delay Between Last PGCx ↓ of Command
Byte to PGDx ↑ by Programming Executive
Programming Executive Command
Processing Time
PGCx Low Time After Programming
Chip Erase Time
Page Erase Time
Row Programming Time
MCLR Rise Time to Enter ICSP™ mode
Data Out Valid from PGCx ↑
Delay Between Last PGCx ↓ and MCLR ↓
MCLR ↓ to V
Delay from First MCLR ↓ to First PGCx ↑
for Key Sequence on PGDx
Delay from Last PGCx ↓ for Key
Sequence on PGDx to Second MCLR ↑
Delay Between PGDx ↓ by Programming
Executive to PGDx Driven by Host
Delay Between Programming Executive
Command Response Words
and V
DD
must be supplied to the V
↑ Setup Time to MCLR ↑
SS
, respectively.
DD
Characteristic
CAP
DDCORE
DD
pins during programming. AV
/V
CAP
pin if the on-chip voltage regulator is disabled. See Section 2.1
V
DDCORE
0.8 V
Min
V
100
100
400
400
100
3.0
4.7
40
40
15
15
40
40
20
25
12
40
40
10
40
23
2
0
1
8
SS
PIC24FJXXXGA0XX
DD
DDCORE
+ 0.1
0.2 V
allowing Flash programming is 2.25V.)
Max
3.60
V
DD
0.4
1.0
50
10
5
2
DD
and AV
DD
Units
mA
ms
ms
ms
ms
ms
μA
pF
μF
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
ns
μs
ns
ns
ns
µs
ns
V
V
V
V
V
s
SS
should always be within ±0.3V
Normal programming
I
I
To meet AC specifications
Required for controller core
OL
OH
= 8.5 mA @ 3.6V
= -3.0 mA @ 3.6V
Conditions
DS39768D-page 49
(1,2)

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