PIC24FJ64GA306-I/MR Microchip Technology, PIC24FJ64GA306-I/MR Datasheet - Page 241

• Manufacturer Part Number: PIC24FJ64GA306-I/MR
• Description: 16-bit, 16 MIPS, 64 KB Flash, 8 KB RAM, 53 I/O, LCD, XLP W/Vbat 64 QFN 9x9x0.9mm
• Manufacturer: Microchip Technology

18.0
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules available
in the PIC24F device family. The UART is a full-duplex,
asynchronous system that can communicate with
peripheral devices, such as personal computers,
LIN/J2602, RS-232 and RS-485 interfaces. The module
also supports a hardware flow control option with the
UxCTS and UxRTS pins, and includes an IrDA
and decoder.
The primary features of the UART module are:
• Full-Duplex, 8 or 9-Bit Data Transmission through
• Even, Odd or No Parity Options (for 8-bit data)
• One or Two Stop bits
• Hardware Flow Control Option with the UxCTS
FIGURE 18-1:
 2010-2011 Microchip Technology Inc.
Note:
the UxTX and UxRX Pins
and UxRTS Pins
Note:
UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
Section 21. “UART” (DS39708). The
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F
information in this data sheet supersedes
the information in the FRM.
The UART inputs and outputs must all be assigned to available RPn/RPIn pins before use. See
“Peripheral Pin Select (PPS)”
Family
UART SIMPLIFIED BLOCK DIAGRAM
Hardware Flow Control
Baud Rate Generator
UARTx Transmitter
UARTx Receiver
Reference
IrDA
®
for more information.
Manual”,
®
encoder
PIC24FJ128GA310 FAMILY
• Fully Integrated Baud Rate Generator with 16-Bit
• Baud Rates Ranging from 15 bps to 1 Mbps at
• 4-Deep, First-In-First-Out (FIFO) Transmit Data
• 4-Deep FIFO Receive Data Buffer
• Parity, Framing and Buffer Overrun Error Detection
• Support for 9-bit mode with Address Detect
• Transmit and Receive Interrupts
• Loopback mode for Diagnostic Support
• Support for Sync and Break Characters
• Supports Automatic Baud Rate Detection
• IrDA
• 16x Baud Clock Output for IrDA Support
A simplified block diagram of the UART is shown in
Figure
important hardware elements:
• Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
Prescaler
16 MIPS
Buffer
(9
th
bit = 1)
®
18-1. The UART module consists of these key
Encoder and Decoder Logic
UxRTS/BCLKx
UxCTS
UxRX
UxTX
DS39996F-page 241
Section 11.4