PIC24FJ64GA306-I/MR Microchip Technology, PIC24FJ64GA306-I/MR Datasheet - Page 75

• Manufacturer Part Number: PIC24FJ64GA306-I/MR
• Description: 16-bit, 16 MIPS, 64 KB Flash, 8 KB RAM, 53 I/O, LCD, XLP W/Vbat 64 QFN 9x9x0.9mm
• Manufacturer: Microchip Technology

5.0
The Direct Memory Access Controller (DMA) is
designed to service high-data-throughput peripherals
operating on the SFR bus, allowing them to access
data memory directly and alleviating the need for CPU
intensive management. By allowing these data inten-
sive peripherals to share their own data path, the main
data bus is also de-loaded, resulting in additional
power savings.
The DMA Controller functions both as a peripheral and
a direct extension of the CPU. It is located on the micro-
controller
DMA-enabled peripherals, with direct access to SRAM.
This partitions the SFR bus into two buses, allowing the
DMA Controller access to the DMA-capable peripher-
als located on the new DMA SFR bus. The controller
serves as a master device on the DMA SFR bus,
controlling data flow from DMA capable peripherals.
FIGURE 5-1:
 2010-2011 Microchip Technology Inc.
Note:
Data
Bus
and Peripherals
To I/O Ports
DIRECT MEMORY ACCESS
CONTROLLER (DMA)
Data RAM
This data sheet summarizes the features
of the PIC24FJ128GA310 family of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
the “PIC24F Family Reference Manual”,
Section 54. “Direct Memory Access
Controller (DMA)” (DS39742). The infor-
mation in this data sheet supersedes the
information in the FRM.
data
bus
DMA FUNCTIONAL BLOCK DIAGRAM
between
DMASRC0
DMADST0
DMACNT0
Channel 0
DMAINT0
DMACH0
the
CPU Execution Monitoring
CPU
DMASRC1
DMACNT1
DMADST1
Channel 1
DMAINT1
DMACH1
Control
PIC24FJ128GA310 FAMILY
Logic
and
DMACON
DMABUF
DMAH
DMAL
The controller also monitors CPU instruction process-
ing directly, allowing it to be aware of when the CPU
requires access to peripherals on the DMA bus, and
automatically relinquishing control to the CPU as
needed. This increases the effective bandwidth for
handling data without DMA operations causing a
processor stall. This makes the controller essentially
transparent to the user.
The DMA Controller has these features:
• Six multiple independent and independently
• Concurrent operation with the CPU (no DMA
• DMA bus arbitration
• Five Programmable Address modes
• Four Programmable Transfer modes
• Four Flexible Internal Data Transfer modes
• Byte or word support for data transfer
• 16-Bit Source and Destination Address register
• 16-Bit Transaction Count register, dynamically
• Upper and Lower Address Limit registers
• Counter half-full level interrupt
• Software triggered transfer
• Null Write mode for symmetric buffer operations
A simplified block diagram of the DMA Controller is
shown if
DMASRC2
DMACNT2
DMADST2
DMAINT2
Channel 4
DMACH2
programmable channels
caused Wait states)
for each channel, dynamically updated and
reloadable
updated and reloadable
Figure
DMASRCn
DMADSTn
DMACNTn
5-1.
DMAINTn
Channel 5
DMACHn
Address Generation
To DMA-Enabled
Peripherals
Data RAM
DS39996F-page 75