PIC24FJ64GA306-I/MR Microchip Technology, PIC24FJ64GA306-I/MR Datasheet - Page 343

• Manufacturer Part Number: PIC24FJ64GA306-I/MR
• Description: 16-bit, 16 MIPS, 64 KB Flash, 8 KB RAM, 53 I/O, LCD, XLP W/Vbat 64 QFN 9x9x0.9mm
• Manufacturer: Microchip Technology

29.2
All PIC24FJ128GA310 family devices power their core
digital logic at a nominal 1.8V. This may create an issue
for designs that are required to operate at a higher
typical voltage, such as 3.3V. To simplify system
design, all devices in the PIC24FJ128GA310 family
incorporate an on-chip regulator that allows the device
to run its core logic from V
This regulator is always enabled. It provides a constant
voltage (1.8V nominal) to the digital core logic, from a
V
MAX
In order to prevent “brown-out” conditions when the
voltage drops too low for the regulator, the Brown-out
Reset occurs. Then the regulator output follows V
with a typical voltage drop of 300 mV.
A low-ESR capacitor (such as ceramic) must be
connected to the V
maintain the stability of the regulator. The recommended
value for the filter capacitor (C
Section 32.1 “DC
FIGURE 29-1:
 2010-2011 Microchip Technology Inc.
DD
Note 1:
. It does not have the capability to boost V
of about 2.1V all the way up to the device’s V
(10 F typ)
On-Chip Voltage Regulator
C
EFC
This is a typical operating voltage. Refer to
Section 32.0 “Electrical Characteristics”
for the full operating ranges of V
3.3V
Characteristics”.
CAP
(1)
CONNECTIONS FOR THE
ON-CHIP REGULATOR
pin
V
V
V
DD
DD
CAP
SS
(Figure
PIC24FJXXXGA3XX
.
EFC
29-1). This helps to
) is provided in
DD
.
DD
PIC24FJ128GA310 FAMILY
levels.
DD
DD
-
29.2.1
The voltage regulator takes approximately 10 s for it
to generate output. During this time, designated as
T
every time the device resumes operation after any
power-down, including Sleep mode. T
mined by the status of the VREGS bit (RCON<8>) and
the WDTWIN Configuration bits (CW3<11:10>). Refer
to
information on T
29.2.2
The on-chip regulator always consumes a small incre-
mental amount of current over I
the device is in Sleep mode, even though the core
digital logic does not require power. To provide addi-
tional savings in applications where power resources
are critical, the regulator can be made to enter Standby
mode on its own whenever the device goes into Sleep
mode. This feature is controlled by the VREGS bit
(RCON<8>). Clearing the VREGS bit enables the
Standby mode. When waking up from Standby mode,
the regulator needs to wait for T
wake-up.
29.2.3
When power-saving modes, such as Sleep and Deep
Sleep are used, PIC24FJ128GA310 family devices
may use a separate low-power, low-voltage/retention
regulator to power critical circuits. This regulator, which
operates at 1.2V nominal, maintains power to data
RAM and the RTCC while all other core digital logic is
powered down. It operates only in Sleep, Deep Sleep
and V
The low-voltage/retention regulator is described in more
detail in
Regulator”.
VREG
Note:
Section 32.0 “Electrical Characteristics”
BAT
, code execution is disabled. T
modes.
Section 10.1.3 “Low-Voltage/Retention
ON-CHIP REGULATOR AND POR
For more information, see
“Electrical
mation in this data sheet supersedes the
information in the FRM.
VOLTAGE REGULATOR STANDBY
MODE
LOW-VOLTAGE/RETENTION
REGULATOR
VREG
.
Characteristics”. The infor-
DD
VREG
/I
PD
DS39996F-page 343
, including when
VREG
to expire before
VREG
Section 32.0
is applied
is deter-
for more