PIC24FJ64GA306-I/MR Microchip Technology, PIC24FJ64GA306-I/MR Datasheet - Page 246

• Manufacturer Part Number: PIC24FJ64GA306-I/MR
• Description: 16-bit, 16 MIPS, 64 KB Flash, 8 KB RAM, 53 I/O, LCD, XLP W/Vbat 64 QFN 9x9x0.9mm
• Manufacturer: Microchip Technology

PIC24FJ128GA310 FAMILY
REGISTER 18-2:
DS39996F-page 246
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
HS = Hardware Settable bit
bit 15,13
bit 14
bit 12
bit 11
bit 10
bit 9
bit 8
Note 1:
URXISEL1
UTXISEL1
R/W-0
R/W-0
2:
3:
The value of the bit only affects the transmit properties of the module when the IrDA
(IREN = 1).
If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See
Section 11.4 “Peripheral Pin Select (PPS)”
The TRMT bit will be active only after two instruction, cycles once the UTXREG is loaded.
UTXISEL<1:0>: Transmission Interrupt Mode Selection bits
11 = Reserved; do not use
10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result, the
01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least
UTXINV: IrDA
IREN = 0:
1 = UxTX is Idle ‘0’
0 = UxTX is Idle ‘1’
IREN = 1:
1 = UxTX is Idle ‘1’
0 = UxTX is Idle ‘0’
Unimplemented: Read as ‘0’
UTXBRK: Transmit Break bit
1 = Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
0 = Sync Break transmission is disabled or completed
UTXEN: Transmit Enable bit
1 = Transmit is enabled, UxTX pin is controlled by UARTx
0 = Transmit is disabled, any pending transmission is aborted and the buffer is reset; UxTX pin is
UTXBF: Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
TRMT: Transmit Shift Register Empty bit (read-only)
1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit Shift Register is not empty, a transmission is in progress or queued
URXISEL0
UTXINV
R/W-0
R/W-0
cleared by hardware upon completion
controlled by the port.
transmit buffer becomes empty
operations are completed
one character open in the transmit buffer)
UxSTA: UARTx STATUS AND CONTROL REGISTER
(1)
®
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
HC = Hardware Clearable bit
Encoder Transmit Polarity Inversion bit
UTXISEL0
ADDEN
R/W-0
R/W-0
(2)
R-1, HSC
RIDLE
U-0
—
for more information.
HSC = Hardware Settable/Clearable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0 HC
R-0, HSC
UTXBRK
PERR
(3)
(1)
UTXEN
R-0, HSC
R/W-0
FERR
 2010-2011 Microchip Technology Inc.
(2)
x = Bit is unknown
R/C-0, HS
R-0, HSC
UTXBF
OERR
®
encoder is enabled
R-1, HSC
R-0, HSC
TRMT
URXDA
(3)
bit 8
bit 0