PIC32MX110F016B-I/SS Microchip Technology, PIC32MX110F016B-I/SS Datasheet - Page 128

• Manufacturer Part Number: PIC32MX110F016B-I/SS
• Description: PIC32, 16KB Flash, 4KB RAM, 40 MHz, CTMU, 4 DMA 28 SSOP .209in TUBE
• Manufacturer: Microchip Technology

PIC32MX1XX/2XX
REGISTER 10-6:
DS61168C-page 128
Legend:
R = Readable bit
-n = Value at POR
bit 31-8 Unimplemented: Read as ‘0’
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
Note 1:
Range
31:24
23:16
15:8
7:0
Bit
2:
3:
4:
5:
6:
31/23/15/7
STALLIF: STALL Handshake Interrupt bit
1 = In Host mode a STALL handshake was received during the handshake phase of the transaction
In Device mode a STALL handshake was transmitted during the handshake phase of the transaction
0 = STALL handshake has not been sent
ATTACHIF: Peripheral Attach Interrupt bit
1 = Peripheral attachment was detected by the USB module
0 = Peripheral attachment was not detected
RESUMEIF: Resume Interrupt bit
1 = K-State is observed on the D+ or D- pin for 2.5 µs
0 = K-State is not observed
IDLEIF: Idle Detect Interrupt bit
1 = Idle condition detected (constant Idle state of 3 ms or more)
0 = No Idle condition detected
TRNIF: Token Processing Complete Interrupt bit
1 = Processing of current token is complete; a read of the U1STAT register will provide endpoint information
0 = Processing of current token not complete
SOFIF: SOF Token Interrupt bit
1 = SOF token received by the peripheral or the SOF threshold reached by the host
0 = SOF token was not received nor threshold reached
UERRIF: USB Error Condition Interrupt bit
1 = Unmasked error condition has occurred
0 = Unmasked error condition has not occurred
R/WC-0, HS
STALLIF
This bit is valid only if the HOSTEN bit is set (see
2.5 µs, and the current bus state is not SE0.
When not in Suspend mode, this interrupt should be disabled.
Clearing this bit will cause the STAT FIFO to advance.
Only error conditions enabled through the U1EIE register will set this bit.
Device mode.
Host mode.
Bit
U-0
U-0
U-0
—
—
—
ATTACHIF
U1IR: USB INTERRUPT REGISTER
30/22/14/6
R/WC-0, HS
Bit
U-0
U-0
U-0
—
—
—
(1)
WC = Write ‘1’ to clear
W = Writable bit
‘1’ = Bit is set
RESUMEIF
29/21/13/5
R/WC-0, HS
Bit
U-0
U-0
U-0
—
—
—
(2)
(2)
Preliminary
(1)
(4)
28/20/12/4
R/WC-0, HS
IDLEIF
Bit
U-0
U-0
U-0
—
—
—
(3)
Register
HS = Hardware Settable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
27/19/11/3
R/WC-0, HS
TRNIF
Bit
U-0
U-0
U-0
—
—
—
10-11), there is no activity on the USB for
(3)
26/18/10/2
R/WC-0, HS
SOFIF
Bit
U-0
U-0
U-0
—
—
—
© 2011 Microchip Technology Inc.
x = Bit is unknown
UERRIF
25/17/9/1
Bit
U-0
U-0
U-0
R-0
—
—
—
(4)
DETACHIF
URSTIF
24/16/8/0
R/WC-0, HS
Bit
U-0
U-0
U-0
—
—
—
(5)
(6)