PIC32MX110F016B-I/SS Microchip Technology, PIC32MX110F016B-I/SS Datasheet - Page 186

• Manufacturer Part Number: PIC32MX110F016B-I/SS
• Description: PIC32, 16KB Flash, 4KB RAM, 40 MHz, CTMU, 4 DMA 28 SSOP .209in TUBE
• Manufacturer: Microchip Technology

PIC32MX1XX/2XX
REGISTER 19-1:
DS61168C-page 186
Legend:
R = Readable bit
-n = Value at POR
bit 31-16 Unimplemented: Read as ‘0’
bit 15
bit 14
bit 13
bit 12-11 ADRMUX<1:0>: Address/Data Multiplexing Selection bits
bit 10
bit 9
bit 8
bit 7-6
bit 5
Range
31:24
23:16
15:8
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
7:0
Bit
2: These bits have no effect when their corresponding pins are used as address lines.
ON: Parallel Master Port Enable bit
1 = PMP enabled
0 = PMP disabled, no off-chip access performed
Unimplemented: Read as ‘0’
SIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
11 = Lower 8 bits of address are multiplexed on PMD<7:0> pins; upper 8 bits are not used
10 = All 16 bits of address are multiplexed on PMD<7:0> pins
01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper bits are on PMA<10:8> and
00 = Address and data appear on separate pins
PMPTTL: PMP Module TTL Input Buffer Select bit
1 = PMP module uses TTL input buffers
0 = PMP module uses Schmitt Trigger input buffer
PTWREN: Write Enable Strobe Port Enable bit
1 = PMWR/PMENB port enabled
0 = PMWR/PMENB port disabled
PTRDEN: Read/Write Strobe Port Enable bit
1 = PMRD/PMWR port enabled
0 = PMRD/PMWR port disabled
CSF<1:0>: Chip Select Function bits
11 = Reserved
10 = PMCS1 function as Chip Select
01 = PMCS1 functions as address bit 14
00 = PMCS1 function as address bit 14
ALP: Address Latch Polarity bit
1 = Active-high (PMALL and PMALH)
0 = Active-low (PMALL and PMALH)
31/23/15/7
SYSCLK cycle immediately following the instruction that clears the module’s ON control bit.
ON
R/W-0
R/W-0
Bit
U-0
U-0
—
—
PMA<14>
CSF<1:0>
(1)
PMCON: PARALLEL PORT CONTROL REGISTER
30/22/14/6
(2)
R/W-0
Bit
U-0
U-0
U-0
—
—
—
W = Writable bit
‘1’ = Bit is set
29/21/13/5
ALP
R/W-0
SIDL
R/W-0
Bit
U-0
U-0
(2)
—
—
(2)
(1)
(2)
Preliminary
28/20/12/4
R/W-0
Bit
U-0
U-0
U-0
—
—
—
ADRMUX<1:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
27/19/11/3
CS1P
R/W-0
R/W-0
Bit
U-0
U-0
—
—
(2)
26/18/10/2
PMPTTL
R/W-0
Bit
U-0
U-0
U-0
—
—
—
© 2011 Microchip Technology Inc.
x = Bit is unknown
PTWREN
25/17/9/1
WRSP
R/W-0
R/W-0
Bit
U-0
U-0
—
—
24/16/8/0
PTRDEN
RDSP
R/W-0
R/W-0
Bit
U-0
U-0
—
—