PIC32MX110F016B-I/SS Microchip Technology, PIC32MX110F016B-I/SS Datasheet - Page 180

• Manufacturer Part Number: PIC32MX110F016B-I/SS
• Description: PIC32, 16KB Flash, 4KB RAM, 40 MHz, CTMU, 4 DMA 28 SSOP .209in TUBE
• Manufacturer: Microchip Technology

PIC32MX1XX/2XX
REGISTER 18-1:
DS61168C-page 180
Legend:
R = Readable bit
-n = Value at POR
bit 31-16 Unimplemented: Read as ‘0’
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9-8
bit 7
bit 6
Note 1:
Range
31:24
23:16
15:8
7:0
Bit
ON: UARTx Enable bit
1 = UARTx is enabled. UARTx pins are controlled by UARTx as defined by UEN<1:0> and UTXEN
0 = UARTx is disabled. All UARTx pins are controlled by corresponding bits in the PORTx, TRISx and LATx
Unimplemented: Read as ‘0’
SIDL: Stop in Idle Mode bit
1 = Discontinue operation when device enters Idle mode
0 = Continue operation in Idle mode
IREN: IrDA Encoder and Decoder Enable bit
1 = IrDA is enabled
0 = IrDA is disabled
RTSMD: Mode Selection for UxRTS Pin bit
1 = UxRTS pin is in Simplex mode
0 = UxRTS pin is in Flow Control mode
Unimplemented: Read as ‘0’
UEN<1:0>: UARTx Enable bits
11 = UxTX, UxRX and UxBCLK pins are enabled and used; UxCTS pin is controlled by corresponding bits
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by corresponding bits
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by
WAKE: Enable Wake-up on Start bit Detect During Sleep Mode bit
1 = Wake-up enabled
0 = Wake-up disabled
LPBACK: UARTx Loopback Mode Select bit
1 = Loopback mode is enabled
0 = Loopback mode is disabled
When using 1:1 PBCLK divisor, the user software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
31/23/15/7
WAKE
ON
R/W-0
R/W-0
control bits
registers; UARTx power consumption is minimal
Bit
U-0
U-0
—
—
in the PORTx register
in the PORTx register
corresponding bits in the PORTx register
(1)
UxMODE: UARTx MODE REGISTER
30/22/14/6
LPBACK
R/W-0
Bit
U-0
U-0
U-0
—
—
—
(1)
‘1’ = Bit is set
W = Writable bit
29/21/13/5
ABAUD
SIDL
R/W-0
R/W-0
Bit
U-0
U-0
—
—
Preliminary
28/20/12/4
RXINV
IREN
R/W-0
R/W-0
Bit
U-0
U-0
—
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
27/19/11/3
RTSMD
BRGH
R/W-0
R/W-0
Bit
U-0
U-0
—
—
26/18/10/2
R/W-0
Bit
U-0
U-0
U-0
—
—
—
PDSEL<1:0>
© 2011 Microchip Technology Inc.
x = Bit is unknown
25/17/9/1
R/W-0
R/W-0
Bit
U-0
U-0
—
—
UEN<1:0>
24/16/8/0
STSEL
R/W-0
R/W-0
Bit
U-0
U-0
—
—