SC16C650BIA44 NXP Semiconductors, SC16C650BIA44 Datasheet
SC16C650BIA44
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SC16C650BIA44 Summary of contents
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SC16C650B 5 V, 3.3 V and 2.5 V UART with 32-byte FIFOs and infrared (IrDA) encoder/decoder Rev. 04 — 14 September 2009 1. General description The SC16C650B is a Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications. ...
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... Prioritized interrupt system controls I Modem control functions (CTS, RTS, DSR, DTR, RI, DCD) 3. Ordering information Table 1. Ordering information Industrial 2 Type number Package Name SC16C650BIA44 PLCC44 SC16C650BIB48 LQFP48 SC16C650BIBS HVQFN32 SC16C650B_4 Product data sheet UART with 32-byte FIFOs and IrDA encoder/decoder 2-stop bit ...
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... NXP Semiconductors 4. Block diagram SC16C650B DATA BUS IOR, IOR AND IOW, IOW CONTROL RESET LOGIC REGISTER CS0, CS1, CS2 SELECT LOGIC AS DDIS INT TXRDY RXRDY INTERRUPT CONTROL LOGIC Fig 1. Block diagram SC16C650B_4 Product data sheet UART with 32-byte FIFOs and IrDA encoder/decoder ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. Fig 3. SC16C650B_4 Product data sheet UART with 32-byte FIFOs and IrDA encoder/decoder RCLK RX 11 SC16C650BIA44 n. CS0 CS1 15 CS2 16 17 BAUDOUT Pin configuration for PLCC44 n. RCLK 5 6 n.c. SC16C650BIB48 CS0 9 10 CS1 CS2 11 BAUDOUT 12 Pin confi ...
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... NXP Semiconductors Fig 4. 5.2 Pin description Table 2. Pin description Symbol Pin PLCC44 LQFP48 HVQFN32 BAUDOUT 17 12 CS0 14 9 CS1 15 10 CS2 CTS 40 38 SC16C650B_4 Product data sheet UART with 32-byte FIFOs and IrDA encoder/decoder terminal 1 index area RCLK 4 SC16C650BIBS BAUDOUT 8 Transparent top view Pin confi ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin PLCC44 LQFP48 HVQFN32 DCD 42 40 DDIS 26 22 DSR 41 39 DTR 37 33 INT 33 30 OUT1 38 34 OUT2 35 31 OUT - - RCLK 10 5 IOR 25 20 IOR 24 19 SC16C650B_4 Product data sheet UART with 32-byte FIFOs and IrDA encoder/decoder ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin PLCC44 LQFP48 HVQFN32 RESET RTS 36 32 RXRDY TXRDY GND 22 18 IOW 21 17 IOW 20 16 SC16C650B_4 Product data sheet UART with 32-byte FIFOs and IrDA encoder/decoder Type Description 24 I Master Reset. When active (HIGH), MR clears most UART registers and sets the levels of various output signals ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin PLCC44 LQFP48 HVQFN32 XTAL1 18 14 [2] XTAL2 19 15 n.c. 1, 12, 23 13, 34 21, 25, 36, 37, 48 [1] HVQFN32 package die supply ground is connected to both GND pin and exposed center pad. GND pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region ...
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... NXP Semiconductors 6.1 Internal registers The SC16C650B provides 17 internal registers for monitoring and control. These registers are shown in standard 16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register (FCR), line status and control registers (LCR/LSR), modem status and control registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), and a user accessible ScratchPad Register (SPR) ...
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... NXP Semiconductors data is delivered to the external CPU. An interrupt is generated whenever the Receive Holding Register (RHR) has not been read following the loading of a character or the receive trigger level has not been reached. Table 4. Selected trigger level (characters 6.3 Hardware flow control When automatic hardware fl ...
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... NXP Semiconductors In the event that the receive buffer is overfilling and flow control needs to be executed, the SC16C650B automatically sends an Xoff message (when enabled) via the serial TX output to the remote modem. The SC16C650B sends the Xoff1/Xoff2 characters as soon as received data passes the programmed trigger level. To clear this condition, the SC16C650B will transmit the programmed Xon1/Xon2 characters as soon as receive data drops below the next low or programmed trigger level ...
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... NXP Semiconductors 6.7 Programmable baud rate generator The SC16C650B supports high speed modem technologies that have increased input data rates by employing data compression schemes. For example, a 33.6 kbit/s modem that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s ISDN modem that supports data compression may need an input data rate of 460 ...
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... NXP Semiconductors Table 5. Using 1.8432 MHz crystal Desired baud rate 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 56000 XTAL1 XTAL2 Fig 6. SC16C650B_4 Product data sheet UART with 32-byte FIFOs and IrDA encoder/decoder Baud rates using 1 ...
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... NXP Semiconductors 6.8 DMA operation The SC16C650B FIFO trigger level provides additional flexibility to the user for block mode operation. The user can optionally operate the transmit and receive FIFOs in the DMA mode (FCR[3]). The DMA mode affects the state of the RXRDY and TXRDY output pins ...
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... NXP Semiconductors In this mode, the receiver and transmitter interrupts are fully operational. The Modem Control Interrupts are also operational. However, the interrupts can only be read using lower four bits of the Modem Status Register (MSR[3:0]) instead of the four Modem Status Register bits 7:4. The interrupts are still controlled by the IER. ...
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... NXP Semiconductors 7. Register descriptions Table 8 The assigned bit functions are more fully defined in Table 8. SC16C650B internal registers Register Default [1] [2] General register set RHR THR IER FCR ISR LCR MCR LSR MSR SPR FF [7] Special register set DLL DLM XX [8] Enhanced register set ...
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... NXP Semiconductors [6] This bit controls the OUT pin in the HVQFN32 package, and OUT1 in the other packages. [7] The Special register set is accessible only when LCR[7] is set to a logic 1. [8] Enhanced Feature Register (EFR), Xon1, Xon2 Xoff1, Xoff2 are accessible only when LCR is set to BFh. ...
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... NXP Semiconductors Table 9. Bit Symbol 2 IER[2] 1 IER[1] 0 IER[0] 7.2.1 IER versus receive FIFO interrupt mode operation When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are enabled, the receive interrupts and register status will reflect the following: • The receive data available interrupts are issued to the external CPU when the FIFO has reached the programmed trigger level ...
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... NXP Semiconductors 7.3 FIFO Control Register (FCR) This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger levels, and select the DMA mode. 7.3.1 DMA mode 7.3.1.1 Mode 0 (FCR bit Set and enable the interrupt for each single transmit or receive operation, and is similar to the 16C450 mode ...
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... NXP Semiconductors Table 10. Bit 3 (cont Table 11. FCR[ Table 12. FCR[ SC16C650B_4 Product data sheet UART with 32-byte FIFOs and IrDA encoder/decoder FIFO Control Register bits description Symbol Description Transmit operation in mode ‘1’: When the SC16C650B is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a logic 1 when the transmit FIFO is completely full ...
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... NXP Semiconductors 7.4 Interrupt Status Register (ISR) The SC16C650B provides six levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced ...
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... NXP Semiconductors 7.5 Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. Table 15. Bit 1:0 SC16C650B_4 Product data sheet ...
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... NXP Semiconductors Table 16. LCR[ Table 17. LCR[ Table 18. LCR[ 7.6 Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. Table 19. Bit Symbol 7 MCR[7] 6 MCR[6] SC16C650B_4 Product data sheet UART with 32-byte FIFOs and IrDA encoder/decoder LCR[5] parity selection ...
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... NXP Semiconductors Table 19. Bit Symbol 5 MCR[5] 4 MCR[4] 3 MCR[3] 2 MCR[2] 1 MCR[1] 0 MCR[0] SC16C650B_4 Product data sheet UART with 32-byte FIFOs and IrDA encoder/decoder Modem Control Register bits description Description INT type select. logic 0 = enable interrupt output mode (normal default condition) logic 1 = enable open source interrupt output mode. Provides shared interrupts by producing a wire-OR output driver capability for interrupts ...
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... NXP Semiconductors 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C650B and the CPU. Table 20. Bit SC16C650B_4 Product data sheet UART with 32-byte FIFOs and IrDA encoder/decoder Line Status Register bits description Symbol Description LSR[7] FIFO data error ...
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... NXP Semiconductors 7.8 Modem Status Register (MSR) This register provides the current state of the control interface signals from the modem, or other peripheral device to which the SC16C650B is connected. Four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a control input from the modem changes state ...
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... NXP Semiconductors 7.9 Scratchpad Register (SPR) The SC16C650B provides a temporary data register to store 8 bits of user information. 7.10 Enhanced Feature Register (EFR) Enhanced features are enabled or disabled using this register. Bits 0 through 4 provide single or dual character software flow control selection. When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words are concatenated into two sequential numbers ...
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... NXP Semiconductors Table 23. Cont [1] When using a software flow control the Xon/Xoff characters cannot be used for data transfer. 7.11 SC16C650B external reset conditions Table 24. Register IER ISR LCR MCR LSR MSR FCR EFR Table 25. Output TX RTS DTR RXRDY TXRDY INT SC16C650B_4 Product data sheet UART with 32-byte FIFOs and IrDA encoder/decoder Software fl ...
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... NXP Semiconductors 8. Limiting values Table 26. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V voltage on any other pin n T ambient temperature amb T storage temperature stg P /pack total power dissipation per package tot 9. Static characteristics Table 27 ...
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... NXP Semiconductors [2] Sleep current might be higher if there is activity on the data bus during Sleep mode. 10. Dynamic characteristics Table 28. Dynamic characteristics +85 C; tolerance of V amb Symbol Parameter t pulse width LOW WL t pulse width HIGH WH f frequency on pin XTAL1 XTAL1 t address strobe width 4w t address set-up time ...
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... NXP Semiconductors Table 28. Dynamic characteristics +85 C; tolerance of V amb Symbol Parameter t delay from start to set 22d interrupt t delay from IOW to transmit 23d start t delay from IOW to reset 24d interrupt t delay from stop to set 25d RXRDY t delay from IOR to reset 26d RXRDY ...
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... NXP Semiconductors 10.1 Timing diagrams CS2 CS1, CS0 t 8d IOR, IOR DDIS Fig 8. General read timing when using AS signal CS2 CS1, CS0 t 14d IOW, IOW Fig 9. General write timing when using AS signal SC16C650B_4 Product data sheet UART with 32-byte FIFOs and IrDA encoder/decoder ...
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... NXP Semiconductors 6s' CS IOR Fig 10. General read timing when AS is tied to GND 6s' CS IOW Fig 11. General write timing when AS is tied to GND SC16C650B_4 Product data sheet UART with 32-byte FIFOs and IrDA encoder/decoder valid address t 7h' active active t 12h t 12d data ...
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... NXP Semiconductors IOW active RTS change of state DTR DCD CTS DSR INT IOR RI Fig 12. Modem input/output timing external clock -------------- - XTAL1 t w clk Fig 13. External clock timing SC16C650B_4 Product data sheet UART with 32-byte FIFOs and IrDA encoder/decoder t 17d change of state t 18d ...
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... NXP Semiconductors RX INT IOR Fig 14. Receive timing RX RXRDY IOR Fig 15. Receive ready timing in non-FIFO mode SC16C650B_4 Product data sheet UART with 32-byte FIFOs and IrDA encoder/decoder start bit data bits ( data bits 6 data bits 7 data bits 16 baud rate clock start bit ...
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... NXP Semiconductors RX RXRDY IOR Fig 16. Receive ready timing in FIFO mode TX INT active IOW Fig 17. Transmit timing SC16C650B_4 Product data sheet UART with 32-byte FIFOs and IrDA encoder/decoder start bit data bits ( start bit data bits ( data bits 6 data bits 7 data bits ...
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... NXP Semiconductors TX active IOW byte #1 TXRDY Fig 18. Transmit ready timing in non-FIFO mode TX IOW active byte #32 TXRDY Fig 19. Transmit ready timing in FIFO mode (DMA mode ‘1’) SC16C650B_4 Product data sheet UART with 32-byte FIFOs and IrDA encoder/decoder start bit data bits ( ...
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... NXP Semiconductors TX data IrDA TX data Fig 20. Infrared transmit timing IrDA RX data RX data Fig 21. Infrared receive timing SC16C650B_4 Product data sheet UART with 32-byte FIFOs and IrDA encoder/decoder UART frame start bit time bit time start Rev. 04 — 14 September 2009 SC16C650B data bits ...
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... NXP Semiconductors 11. Package outline PLCC44: plastic leaded chip carrier; 44 leads pin 1 index DIMENSIONS (mm dimensions are derived from the original inch dimensions UNIT max. min. 4.57 0.53 mm 0.51 0.25 3.05 4.19 0.33 0.180 0.021 inches 0.02 0.01 0.12 0.165 0.013 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT313-2 136E05 Fig 23 ...
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... NXP Semiconductors HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 0.85 mm terminal 1 index area terminal 1 index area 32 DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 12. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 12.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 12.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... SC16C650B_4 20090914 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • DIP40 package option (type number SC16C650BIN40) removed ...
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... NXP Semiconductors Table 32. Revision history …continued Document ID Release date • Modifications: Section 2 pins”, and added • Table 2 “Pin – added (new) – Description for signal DDIS changed from “DDIS is active (LOW) when the CPU is not reading data. When active, DDIS can disable an external transceiver.” to “DDIS is active (LOW) when the CPU is reading data. When inactive (HIGH), DDIS can disable an external transceiver.” ...
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... NXP Semiconductors Table 32. Revision history …continued Document ID Release date • Modifications: Table 27 “Static (continued) – table title changed (was “DC electrical characteristics”) – descriptive text below table title changed from “ – symbol “V – symbol “V – parameter description for V – ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 8 6.1 Internal registers 6.2 FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.3 Hardware flow control . . . . . . . . . . . . . . . . . . . 10 6.4 Software flow control . . . . . . . . . . . . . . . . . . . 10 6.5 Special feature software flow control . . . . . . . 11 6 ...